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1. 发明申请

US20120286819A1 MOS TEST STRUCTURE, METHOD FOR FORMING MOS TEST STRUCTURE AND METHOD FOR PERFORMING WAFER ACCEPTANCE TEST 有权
标题翻译： MOS测试结构，形成MOS测试结构的方法和执行波形接受测试的方法
公开(公告)号：US20120286819A1
公开(公告)日：2012-11-15
申请号：US13105913
申请日：2011-05-12
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： G01R31/26 , H01L21/28 , H01L23/48
CPC分类号： H01L22/34 , G01R31/02 , G01R31/26 , G01R31/2644 , G01R31/2831
摘要： A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.
摘要翻译：公开了MOS测试结构。划线区域设置在具有与第一侧相对的第一侧和第二侧的基板上。外延层设置在第一侧上，掺杂阱设置在外延层上，并且掺杂区域设置在掺杂阱上。第一深度的沟槽栅极设置在掺杂区域，掺杂阱和划线区域中。导电材料填充测试，通过该测试具有覆盖测试通孔的内壁的第二深度和隔离，并且设置在掺杂区域，掺杂阱，外延层和划线区域中，以电连接到外延层，使得测试通孔能够一起测试外延层和衬底。

2. 发明申请

US20050130066A1 Method of forming single sided conductor and semiconductor device having the same 审中-公开
标题翻译：形成单面导体的方法和具有该单面导体的半导体器件
公开(公告)号：US20050130066A1
公开(公告)日：2005-06-16
申请号：US10731133
申请日：2003-12-10
申请人： Chin-Te Kuo , Jeng Lin , Shian-Jyh Lin , Tsan Lu
发明人： Chin-Te Kuo , Jeng Lin , Shian-Jyh Lin , Tsan Lu
IPC分类号： G03F7/00 , H01L21/32 , H01L21/768 , H01L21/8242
CPC分类号： H01L27/10867 , H01L21/32 , H01L21/76831 , H01L21/76877
摘要： A method of forming a single sided conductor and a semiconductor device having the same is provided. The method includes providing a substrate having an opening. The opening exposes a sidewall and an opening base surface. A tilted mask layer is formed in the opening. The tilted mask layer exposes the sidewall and a portion of the opening base surface. A dielectric layer is formed on the exposed sidewall and the exposed opening base surface. Then, the tilted mask layer is removed, and a conductive layer is formed over the substrate.
摘要翻译：提供了形成单面导体的方法和具有该单面导体的半导体器件。该方法包括提供具有开口的基底。开口露出侧壁和开口底面。在开口中形成倾斜的掩模层。倾斜的掩模层暴露侧壁和开口底面的一部分。在暴露的侧壁和暴露的开口基底表面上形成介电层。然后，去除倾斜的掩模层，并且在衬底上形成导电层。

3. 发明申请

US20120298992A1 TEST LAYOUT STRUCTURE 审中-公开
标题翻译：测试布局结构
公开(公告)号：US20120298992A1
公开(公告)日：2012-11-29
申请号：US13117126
申请日：2011-05-26
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/544
CPC分类号： H01L22/34
摘要： A test layout structure includes a substrate, a first oxide region of a first height, a second oxide region of a second height, a plurality of border regions, and a test layout pattern. The first oxide region is disposed on the substrate. The second oxide region is also disposed on the substrate and adjacent to the first oxide region. The first height is substantially different from the second height. A plurality of border regions are disposed between the first oxide region and the second oxide region. The test layout pattern includes a plurality of individual sections. A test region is disposed between two of the adjacent individual sections which are parallel to each other.
摘要翻译：测试布局结构包括基板，第一高度的第一氧化物区域，第二高度的第二氧化物区域，多个边界区域和测试布局图案。第一氧化物区域设置在基板上。第二氧化物区域也设置在衬底上并与第一氧化物区域相邻。第一高度与第二高度大致不同。多个边界区域设置在第一氧化物区域和第二氧化物区域之间。测试布局图案包括多个单独的部分。测试区域设置在彼此平行的两个相邻的单独部分之间。

4. 发明申请

US20120288683A1 PROTUBERANT STRUCTURE AND METHOD FOR MAKING THE SAME 审中-公开
标题翻译：制备该方法的制备方法及方法
公开(公告)号：US20120288683A1
公开(公告)日：2012-11-15
申请号：US13104943
申请日：2011-05-10
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B32B3/00 , B05D5/02
CPC分类号： H01L21/0338 , B81B2203/0361 , B81B2203/0384 , B81C1/00103 , H01L21/0337 , H01L21/28123 , H01L29/42376 , Y10T428/24612
摘要： The protuberant structure of the present invention includes a substrate and a protrusion disposed on the substrate. The protrusion has a top side, a bottom side and a tapered side wall disposed between the top side and the bottom side. The top side has an extremely small top width which is not greater than 32 nm.
摘要翻译：本发明的突出结构包括基板和设置在基板上的突起。突起具有设置在顶侧和底侧之间的顶侧，底侧和锥形侧壁。顶侧具有不大于32nm的非常小的顶部宽度。

5. 发明申请

US20120286352A1 TRENCH MOS STRUCTURE AND METHOD FOR MAKING THE SAME 有权
标题翻译： TRENCH MOS结构及其制造方法
公开(公告)号：US20120286352A1
公开(公告)日：2012-11-15
申请号：US13104924
申请日：2011-05-10
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0649 , H01L29/0696 , H01L29/1095 , H01L29/66734
摘要： A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.
摘要翻译：提供沟槽MOS结构。沟槽MOS结构包括保护环内的衬底，外延层，沟槽，栅极隔离，沟槽栅极，保护环和加强结构。衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。外延层具有第一导电类型并且设置在第一侧。沟槽设置在外延层中。栅极隔离覆盖沟槽的内壁。沟槽栅设置在沟槽中并且具有第一导电类型。保护环具有第二导电类型并且设置在外延层内。加强结构具有电绝缘材料并且设置在保护环内。

6. 发明授权

US08912595B2 Trench MOS structure and method for forming the same 有权
标题翻译：沟槽MOS结构及其形成方法
公开(公告)号：US08912595B2
公开(公告)日：2014-12-16
申请号：US13106852
申请日：2011-05-12
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L29/423 , H01L29/66 , H01L21/308
CPC分类号： H01L29/7813 , H01L21/3083 , H01L29/4236 , H01L29/66666 , H01L29/66734 , H01L29/7827
摘要： A trench MOS structure is disclosed. The trench MOS structure includes a substrate, an epitaxial layer, a doping well, a doping region and a trench gate. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. The trench gate is partially disposed in the doping region. The trench gate has a bottle shaped profile with a top section smaller than a bottom section, both are partially disposed in the doping well. The bottom section of two adjacent trench gates results in a higher electrical field around the trench MOS structures.
摘要翻译：公开了一种沟槽MOS结构。沟槽MOS结构包括衬底，外延层，掺杂阱，掺杂区和沟槽栅。衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。外延层具有第一导电类型并且设置在第一侧。掺杂阱具有第二导电类型并且设置在外延层上。掺杂区域具有第一导电类型并且被布置在掺杂阱上。沟槽栅极部分地设置在掺杂区域中。沟槽门具有瓶形轮廓，其顶部部分小于底部部分，都部分地设置在掺杂井中。两个相邻沟槽栅极的底部部分导致沟槽MOS结构周围的较高电场。

7. 发明授权

US08816715B2 MOS test structure, method for forming MOS test structure and method for performing wafer acceptance test 有权
标题翻译： MOS测试结构，用于形成MOS测试结构的方法和用于进行晶片验收测试的方法
公开(公告)号：US08816715B2
公开(公告)日：2014-08-26
申请号：US13105913
申请日：2011-05-12
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： G01R31/02 , G01R31/26 , H01L21/66 , G01R31/28
CPC分类号： H01L22/34 , G01R31/02 , G01R31/26 , G01R31/2644 , G01R31/2831
摘要： A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.
摘要翻译：公开了MOS测试结构。划线区域设置在具有与第一侧相对的第一侧和第二侧的基板上。外延层设置在第一侧上，掺杂阱设置在外延层上，并且掺杂区域设置在掺杂阱上。第一深度的沟槽栅极设置在掺杂区域，掺杂阱和划线区域中。导电材料填充测试，通过该测试具有覆盖测试通孔的内壁的第二深度和隔离，并且设置在掺杂区域，掺杂阱，外延层和划线区域中，以电连接到外延层，使得测试通孔能够一起测试外延层和衬底。

8. 发明授权

US08692318B2 Trench MOS structure and method for making the same 有权
标题翻译：沟槽MOS结构和制作方法
公开(公告)号：US08692318B2
公开(公告)日：2014-04-08
申请号：US13104924
申请日：2011-05-10
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0649 , H01L29/0696 , H01L29/1095 , H01L29/66734
摘要： A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.
摘要翻译：提供沟槽MOS结构。沟槽MOS结构包括保护环内的衬底，外延层，沟槽，栅极隔离，沟槽栅极，保护环和加强结构。衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。外延层具有第一导电类型并且设置在第一侧。沟槽设置在外延层中。栅极隔离覆盖沟槽的内壁。沟槽栅设置在沟槽中并且具有第一导电类型。保护环具有第二导电类型并且设置在外延层内。加强结构具有电绝缘材料并且设置在保护环内。

9. 发明申请

US20120286402A1 PROTUBERANT STRUCTURE AND METHOD FOR MAKING THE SAME 审中-公开
标题翻译：制备该方法的制备方法及方法
公开(公告)号：US20120286402A1
公开(公告)日：2012-11-15
申请号：US13105910
申请日：2011-05-12
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/06 , H01L21/302 , H01L23/48
CPC分类号： H01L21/0337 , B81B2203/0361 , B81B2203/0392 , B81C1/00103 , H01L21/0338 , H01L21/28123
摘要： A cuboidal protuberant structure is provided. The cuboidal protuberant structure includes a substrate and a protrusion disposed on the substrate. The protrusion has a vertical side wall with a rounded corner, a protuberant width and a protuberant length. At least one of the protuberant width and the protuberant length is not greater than 33 nm.
摘要翻译：提供立方形隆起结构。立方体隆起结构包括基板和设置在基板上的突起。突起具有垂直侧壁，其具有圆角，突出宽度和突出长度。突出宽度和突出长度中的至少一个不大于33nm。

10. 发明申请

US20120286353A1 TRENCH MOS STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译： TRENCH MOS结构及其形成方法
公开(公告)号：US20120286353A1
公开(公告)日：2012-11-15
申请号：US13106852
申请日：2011-05-12
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/7813 , H01L21/3083 , H01L29/4236 , H01L29/66666 , H01L29/66734 , H01L29/7827
摘要： A trench MOS structure is disclosed. The trench MOS structure includes a substrate, an epitaxial layer, a doping well, a doping region and a trench gate. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. The trench gate is partially disposed in the doping region. The trench gate has a bottle shaped profile with a top section smaller than a bottom section, both are partially disposed in the doping well. The bottom section of two adjacent trench gates results in a higher electrical field around the trench MOS structures.
摘要翻译：公开了一种沟槽MOS结构。沟槽MOS结构包括衬底，外延层，掺杂阱，掺杂区和沟槽栅。衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。外延层具有第一导电类型并且设置在第一侧。掺杂阱具有第二导电类型并且设置在外延层上。掺杂区域具有第一导电类型并且被布置在掺杂阱上。沟槽栅极部分地设置在掺杂区域中。沟槽门具有瓶形轮廓，其顶部部分小于底部部分，都部分地设置在掺杂井中。两个相邻沟槽栅极的底部部分导致沟槽MOS结构周围的较高电场。

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