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1. 发明授权

US07361546B2 Method of forming conductive stud on vertical memory device 有权
标题翻译：在垂直存储设备上形成导电螺柱的方法
公开(公告)号：US07361546B2
公开(公告)日：2008-04-22
申请号：US10704911
申请日：2003-11-12
申请人： Shian-Jyh Lin , Chia-Sheng Yu , Wen-Sung Tsou
发明人： Shian-Jyh Lin , Chia-Sheng Yu , Wen-Sung Tsou
IPC分类号： H01L21/8242
CPC分类号： H01L21/7684 , H01L21/76877 , H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A method of forming a conductive stud is provided. The method includes providing a substrate which has an upper surface and an opening. The opening exposes a portion of a vertical memory device. A conductive layer is formed over the substrate to fill the opening. A chemical mechanical polishing is performed on the conductive layer to form a conductive stud having an upper surface substantially lower than the upper surface of the substrate.
摘要翻译：提供一种形成导电柱的方法。该方法包括提供具有上表面和开口的基底。开口暴露垂直存储器件的一部分。导电层形成在衬底上以填充开口。在导电层上进行化学机械抛光以形成具有基本上低于衬底的上表面的上表面的导电柱。

2. 发明申请

US20050101141A1 Method of forming conductive stud on vertical memory device 有权
标题翻译：在垂直存储设备上形成导电螺柱的方法
公开(公告)号：US20050101141A1
公开(公告)日：2005-05-12
申请号：US10704911
申请日：2003-11-12
申请人： Shian-Jyh Lin , Chia-Sheng Yu , Wen-Sung Tsou
发明人： Shian-Jyh Lin , Chia-Sheng Yu , Wen-Sung Tsou
IPC分类号： H01L21/44 , H01L21/461 , H01L21/768 , H01L21/8242
CPC分类号： H01L21/7684 , H01L21/76877 , H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A method of forming a conductive stud is provided. The method includes providing a substrate which has an upper surface and an opening. The opening exposes a portion of a vertical memory device. A conductive layer is formed over the substrate to fill the opening. A chemical mechanical polishing is performed on the conductive layer to form a conductive stud having an upper surface substantially lower than the upper surface of the substrate.
摘要翻译：提供一种形成导电柱的方法。该方法包括提供具有上表面和开口的基底。开口暴露垂直存储器件的一部分。导电层形成在衬底上以填充开口。在导电层上进行化学机械抛光以形成具有基本上低于衬底的上表面的上表面的导电柱。

3. 发明授权

US07078307B2 Method for manufacturing single-sided buried strap in semiconductor devices 有权
标题翻译：在半导体器件中制造单面埋入带的方法
公开(公告)号：US07078307B2
公开(公告)日：2006-07-18
申请号：US10940761
申请日：2004-09-15
申请人： Shian-Jyh Lin , Chia-Sheng Yu
发明人： Shian-Jyh Lin , Chia-Sheng Yu
IPC分类号： H01L21/20
CPC分类号： H01L27/10867
摘要： A method for manufacturing a single-ended buried strap used in semiconductor devices is disclosed. According to the present invention, a trench capacitor structure is formed in a semiconductor substrate, wherein the trench capacitor structure has a contact surface lower than a surface of the semiconductor substrate such that a recess is formed. Then, an insulative layer is formed on a sidewall of the recess. Next, impurities are implanted into a portion of the insulative layer, and the impurity-containing insulative layer is thereafter removed such that at least a portion of the contact surface and a portion of sidewall of the recess are exposed. A buried strap is sequentially formed on the exposed sidewall of the recess to be in contact with the exposed contact surface.
摘要翻译：公开了一种制造半导体器件中使用的单端掩埋带的方法。根据本发明，在半导体衬底中形成沟槽电容器结构，其中沟槽电容器结构具有比半导体衬底的表面低的接触表面，从而形成凹部。然后，在凹部的侧壁上形成绝缘层。接下来，将杂质注入到绝缘层的一部分中，然后去除含杂质的绝缘层，使得接触表面的至少一部分和凹部的侧壁的一部分露出。在凹部的暴露的侧壁上依次形成埋设的带子，以与暴露的接触表面接触。

4. 发明申请

US20050116275A1 TRENCH CAPACITOR STRUCTURE 有权
标题翻译： TRENCH电容结构
公开(公告)号：US20050116275A1
公开(公告)日：2005-06-02
申请号：US10707264
申请日：2003-12-02
申请人： Shian-Jyh Lin , Sam Liao , Chia-Sheng Yu
发明人： Shian-Jyh Lin , Sam Liao , Chia-Sheng Yu
IPC分类号： H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/94
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/66181 , H01L29/945
摘要： Afin-type trench capacitor structure includes a buried plate diffused into a silicon substrate. The buried plate, which surrounds a bottle-shaped lower portion of the trench capacitor structure, is electrically connected to an upwardly extending annular poly electrode, thereby enabling the buried plate and the annular poly electrode to constitute a large-area capacitor electrode of the trench capacitor structure. A capacitor storage node consisting of a surrounding conductive layer, a central conductive layer and a collar conductive layer encompasses the upwardly extending annular poly electrode. A first capacitor dielectric layer isolates the capacitor storage node from the buried plate. A second capacitor dielectric layer and a third capacitor dielectric layer isolate the upwardly extending annular poly electrode from the capacitor storage node.
摘要翻译： Afin型沟槽电容器结构包括扩散到硅衬底中的掩埋板。包围沟槽电容器结构的瓶形下部的掩埋板电连接到向上延伸的环状聚电极，从而使掩埋板和环形聚电极能够构成沟槽的大面积电容器电极电容器结构。由周围的导电层，中心导电层和环状导电层组成的电容器存储节点包围向上延伸的环形多晶电极。第一电容器电介质层将电容器存储节点与掩埋板隔离。第二电容器电介质层和第三电容器介电层将电容器存储节点上的向上延伸的环形多晶硅电极隔离。

5. 发明申请

US20050164446A1 Method for manufacturing single-sided buried strap in semiconductor devices 有权
标题翻译：在半导体器件中制造单面埋入带的方法
公开(公告)号：US20050164446A1
公开(公告)日：2005-07-28
申请号：US10940761
申请日：2004-09-15
申请人： Shian-Jyh Lin , Chia-Sheng Yu
发明人： Shian-Jyh Lin , Chia-Sheng Yu
IPC分类号： H01L21/306 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L21/8244
CPC分类号： H01L27/10867
摘要： A method for manufacturing a single-ended buried strap used in semiconductor devices is disclosed. According to the present invention, a trench capacitor structure is formed in a semiconductor substrate, wherein the trench capacitor structure has a contact surface lower than a surface of the semiconductor substrate such that a recess is formed. Then, an insulative layer is formed on a sidewall of the recess. Next, impurities are implanted into a portion of the insulative layer, and the impurity-containing insulative layer is thereafter removed such that at least a portion of the contact surface and a portion of sidewall of the recess are exposed. A buried strap is sequentially formed on the exposed sidewall of the recess to be in contact with the exposed contact surface.
摘要翻译：公开了一种制造半导体器件中使用的单端掩埋带的方法。根据本发明，在半导体衬底中形成沟槽电容器结构，其中沟槽电容器结构具有比半导体衬底的表面低的接触表面，从而形成凹部。然后，在凹部的侧壁上形成绝缘层。接下来，将杂质注入到绝缘层的一部分中，然后去除含杂质的绝缘层，使得接触表面的至少一部分和凹部的侧壁的一部分露出。在凹部的暴露的侧壁上依次形成埋设的带子，以与暴露的接触表面接触。

6. 发明授权

US06989561B2 Trench capacitor structure 有权
标题翻译：沟槽电容器结构
公开(公告)号：US06989561B2
公开(公告)日：2006-01-24
申请号：US10707264
申请日：2003-12-02
申请人： Shian-Jyh Lin , Sam Liao , Chia-Sheng Yu
发明人： Shian-Jyh Lin , Sam Liao , Chia-Sheng Yu
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/66181 , H01L29/945
摘要： Afin-type trench capacitor structure includes a buried plate diffused into a silicon substrate. The buried plate, which surrounds a bottle-shaped lower portion of the trench capacitor structure, is electrically connected to an upwardly extending annular poly electrode, thereby enabling the buried plate and the annular poly electrode to constitute a large-area capacitor electrode of the trench capacitor structure. A capacitor storage node consisting of a surrounding conductive layer, a central conductive layer and a collar conductive layer encompasses the upwardly extending annular poly electrode. A first capacitor dielectric layer isolates the capacitor storage node from the buried plate. A second capacitor dielectric layer and a third capacitor dielectric layer isolate the upwardly extending annular poly electrode from the capacitor storage node.
摘要翻译： Afin型沟槽电容器结构包括扩散到硅衬底中的掩埋板。包围沟槽电容器结构的瓶形下部的掩埋板电连接到向上延伸的环状聚电极，从而使掩埋板和环形聚电极能够构成沟槽的大面积电容器电极电容器结构。由周围的导电层，中心导电层和环状导电层组成的电容器存储节点包围向上延伸的环状多晶电极。第一电容器电介质层将电容器存储节点与掩埋板隔离。第二电容器电介质层和第三电容器介电层将电容器存储节点上的向上延伸的环形多晶硅电极隔离。

7. 发明授权

US07094672B2 Method for forming self-aligned contact in semiconductor device 有权
标题翻译：在半导体器件中形成自对准接触的方法
公开(公告)号：US07094672B2
公开(公告)日：2006-08-22
申请号：US10940772
申请日：2004-09-15
申请人： Meng-Hung Chen , Shian-Jyh Lin , Chia-Sheng Yu
发明人： Meng-Hung Chen , Shian-Jyh Lin , Chia-Sheng Yu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897
摘要： A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method includes the steps of forming a first insulating layer that includes a nitride along a profile of a gate structure and a junction region, forming a temporary layer that has a doped oxide on the first insulting layer, removing a portion of the temporary layer by performing a selective etch of the oxide with a mask while leaving a plug portion of the temporary layer over the junction region, forming a second insulting layer that has an undoped oxide in a region where the portion of the temporary layer is removed, removing the plug portion by performing a selective etch of the undoped oxide to form a contact hole, removing a portion of the first insulating layer at a bottom of the contact hole, and forming a conductive contact ins the contact hole.
摘要翻译：一种用于在设置有多个场效应晶体管的半导体衬底上形成自对准接触的方法。该方法包括以下步骤：沿栅极结构和结区域的轮廓形成包括氮化物的第一绝缘层，在第一绝缘层上形成具有掺杂氧化物的临时层，通过以下步骤除去临时层的一部分：用掩模进行氧化物的选择性蚀刻，同时将临时层的插塞部分留在接合区域上，形成在临时层的部分被去除的区域中具有未掺杂氧化物的第二绝缘层，去除插塞通过对未掺杂的氧化物进行选择性蚀刻以形成接触孔，在接触孔的底部除去第一绝缘层的一部分，以及在接触孔中形成导电接触。

8. 发明授权

US06867091B1 Method for forming deep trench capacitor with liquid phase deposition oxide as collar oxide 有权
公开(公告)号：US06867091B1
公开(公告)日：2005-03-15
申请号：US10833066
申请日：2004-04-28
申请人： Sam Liao , Shian-Jyh Lin , Chia-Sheng Yu
发明人： Sam Liao , Shian-Jyh Lin , Chia-Sheng Yu
IPC分类号： H01L21/334 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A method for forming a deep trench capacitor mainly utilizes a liquid phase deposition (LPD) oxide to form a collar oxide layer in the trench, followed by forming a conductive layer serving as an upper electrode of the deep trench capacitor, thereby avoiding collar oxide residue in the conductive layer and thus forming good electrical connection. And, the method of the present invention does not need a dry etch to remove the unnecessary collar oxide layer such that the process can be simplified.

9. 发明申请

US20050245040A1 Method for forming deep trench capacitor with liquid phase deposition oxide as collar oxide 审中-公开
标题翻译：用作为环氧化物的液相沉积氧化物形成深沟槽电容器的方法
公开(公告)号：US20050245040A1
公开(公告)日：2005-11-03
申请号：US11039843
申请日：2005-01-24
申请人： Sam Liao , Shian-Jyh Lin , Chia-Sheng Yu
发明人： Sam Liao , Shian-Jyh Lin , Chia-Sheng Yu
IPC分类号： H01L21/334 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A method for forming a deep trench capacitor mainly utilizes a liquid phase deposition (LPD) oxide to form a collar oxide layer in the trench, followed by forming a conductive layer serving as an upper electrode of the deep trench capacitor, thereby avoiding collar oxide residue in the conductive layer and thus forming good electrical connection. And, the method of the present invention does not need a dry etch to remove the unnecessary collar oxide layer such that the process can be simplified.
摘要翻译：形成深沟槽电容器的方法主要利用液相沉积（LPD）氧化物在沟槽中形成环状氧化物层，随后形成用作深沟槽电容器的上电极的导电层，从而避免环氧化物残留物在导电层中，从而形成良好的电连接。而且，本发明的方法不需要干蚀刻来去除不需要的环形氧化物层，从而可以简化该方法。

10. 发明申请

US20050239282A1 Method for forming self-aligned contact in semiconductor device 有权
标题翻译：在半导体器件中形成自对准接触的方法
公开(公告)号：US20050239282A1
公开(公告)日：2005-10-27
申请号：US10940772
申请日：2004-09-15
申请人： Meng-Hung Chen , Shian-Jyh Lin , Chia-Sheng Yu
发明人： Meng-Hung Chen , Shian-Jyh Lin , Chia-Sheng Yu
IPC分类号： H01L21/4763 , H01L21/60
CPC分类号： H01L21/76897
摘要： A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of forming a first insulating layer comprising a nitride along a profile of a gate structure and a junction region, forming a temporary layer comprising a doped oxide on the first insulating layer, removing a portion of the temporary layer by performing a selective etch of the oxide with a mask while leaving a plug portion of the temporary layer over the junction region, forming a second insulating layer comprising an undoped oxide in a region where the portion of the temporary layer is removed, removing the plug portion by performing a selective etch of the undoped oxide to form a contact hole, removing a portion of the first insulating layer at a bottom of the contact hole, and forming a conductive contact in the contact hole.
摘要翻译：一种用于在设置有多个场效应晶体管的半导体衬底上形成自对准接触的方法。该方法包括以下步骤：沿着栅极结构和结区的轮廓形成包括氮化物的第一绝缘层，在第一绝缘层上形成包括掺杂氧化物的临时层，通过执行临时层去除一部分临时层用掩模选择性地蚀刻氧化物，同时将临时层的插塞部分留在接合区域上，形成第二绝缘层，该第二绝缘层包括去除部分临时层的区域中的未掺杂的氧化物，通过执行对未掺杂的氧化物进行选择性蚀刻以形成接触孔，在接触孔的底部除去第一绝缘层的一部分，以及在接触孔中形成导电接触。

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