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31. 发明授权

US5734655A Distributed type switching system 失效
公开(公告)号：US5734655A
公开(公告)日：1998-03-31
申请号：US435961
申请日：1995-05-05
申请人： Yoshito Sakurai , Shinobu Gohara , Kenichi Ohtsuki , Takao Kato , Hiroshi Kuwahara , Eiichi Amada
发明人： Yoshito Sakurai , Shinobu Gohara , Kenichi Ohtsuki , Takao Kato , Hiroshi Kuwahara , Eiichi Amada
IPC分类号： H04L12/54 , H04L12/64 , H04L12/70 , H04L12/931 , H04L12/933 , H04L12/935 , H04L12/937 , H04L12/947 , H04Q11/04 , H04Q11/06
CPC分类号： H04L49/30 , H04L12/56 , H04L12/5601 , H04L12/6402 , H04L49/101 , H04L49/106 , H04L49/15 , H04L49/1553 , H04L49/1584 , H04L49/255 , H04L49/256 , H04L49/3081 , H04L49/309 , H04L49/35 , H04Q11/0407 , H04Q11/0421 , H04Q11/06 , H04J2203/0012 , H04L2012/5651 , H04L2012/5652 , H04L2012/5681 , H04L2012/6481 , H04L49/205 , H04L49/25 , H04L49/254 , H04L49/3009 , H04L49/3018
摘要： A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetrmined period and time slots contained in each frame to carry blocks.

32. 发明授权

US5247518A High-speed ring lan system 失效
标题翻译：高速环网系统
公开(公告)号：US5247518A
公开(公告)日：1993-09-21
申请号：US819821
申请日：1992-01-13
申请人： Yoshihiro Takiyasu , Toshiki Tanaka , Taihei Suzuki , Eiichi Amada , Yukiji Yamauchi , Mitsuhiro Yamaga , Matsuaki Terada , Kunio Hiyama
发明人： Yoshihiro Takiyasu , Toshiki Tanaka , Taihei Suzuki , Eiichi Amada , Yukiji Yamauchi , Mitsuhiro Yamaga , Matsuaki Terada , Kunio Hiyama
IPC分类号： H04J3/08 , H04J3/16 , H04L12/43 , H04L12/56 , H04Q11/04
CPC分类号： H04Q11/0478 , H04J3/08 , H04J3/1617 , H04L12/43 , H04J2203/0042 , H04J2203/0089 , H04L2012/5652 , H04L2012/5672
摘要： A high-speed ring LAN capable of accommodating at least one public network having a signal transmission rate of 155.57 MHz, and at least one sub-LAN having a signal transmission rate of 100 MHz. The high-speed LAN has a signal transmission rate of 155.52 Mbps .times.n (n is an even number). SONET (Synchronous Optical NETwork) subframes each comprising a 9 bytes .times.9 section overhead area and a 261 bytes .times.9 virtual container 4 (VC-4) area flow in a time-divisional n-multiplexed format. The respective node devices inserted in the transmission path have one or more ports to accommodate sub-LANs or public networks. Information is exchanged in units of a fixed-length packet between a received SONET subframe and an asynchronous port whereas information is exchanged in units of a byte between the SONET subframe and a synchronous port.
摘要翻译：能够容纳具有155.57MHz的信号传输速率的至少一个公共网络的高速环形LAN以及信号传输速率为100MHz的至少一个子LAN。高速LAN的信号传输速率为155.52Mbps xn（n为偶数）。 SONET（同步光网络）子帧，每个子帧包括时分多路复用格式的9字节×9部分开销区域和261字节×9虚拟容器4（VC-4）区域流。插入传输路径中的各个节点设备具有一个或多个端口以适应子LAN或公共网络。信息以接收的SONET子帧和异步端口之间的固定长度分组为单位进行交换，而以SONET子帧和同步端口之间的字节为单位交换信息。

33. 发明授权

US5241543A Independent clocking local area network and nodes used for the same 失效
标题翻译：独立时钟局域网和节点使用相同
公开(公告)号：US5241543A
公开(公告)日：1993-08-31
申请号：US672640
申请日：1991-03-20
申请人： Eiichi Amada , Kunio Hiyama , Naoya Kobayashi , Yoshihiro Takiyasu , Yasuhiko Hatekeyama , Haruyuki Nakayama
发明人： Eiichi Amada , Kunio Hiyama , Naoya Kobayashi , Yoshihiro Takiyasu , Yasuhiko Hatekeyama , Haruyuki Nakayama
IPC分类号： H04J3/06 , H04J3/08 , H04J3/16 , H04L12/42 , H04L12/43 , H04L12/56 , H04Q11/04
CPC分类号： H04J3/0623 , H04J3/0626 , H04J3/0647 , H04J3/08 , H04J3/1617 , H04L12/422 , H04L12/43 , H04Q11/0478 , H04J2203/0042 , H04J2203/0082 , H04J2203/0089 , H04J3/0685 , H04L2012/5652 , H04L2012/5672
摘要： In a local area network composed of transmission lines for interconnecting a plurality of subordinate networks including synchronous apparatuses and a plurality of nodes which connect the subordinate networks to the transmission lines, information is transferred using a fixed length frame, a clock source which generates an independent clock signal and a circuit which generates a fixed length frame with the oscillation frequency of the clock source as a reference are provided in each node so as to adopt an independent clocking system, and distribution of a common synchronizing clock required for synchronous apparatuses is made by transmission while embedding transition point information of a synchronizing clock in a specific space in the fixed length frame. Further, each node generates a fixed length transmission frame with an independent clock signal, and on the other hand, there are provided in each node, from the requirement that information quantity applied to a network is made constant, a circuit for extracting a received clock, a storage device for storing received information temporarily, and an information outgoing quantity control circuit in which information quantity which is sent out in one frame is increased when the information quantity stored in the storage device becomes more than a predetermined first reference value and information quantity which is sent out in one frame is decreased when the information quantity stored in the storage device becomes less than a predetermined second reference value.
摘要翻译：在由包括同步装置的多个下属网络和将下属网络连接到传输线路的多个节点互连的传输线路构成的局域网中，使用固定长度的帧传送信息，产生独立的时钟源时钟信号和以时钟源的振荡频率为基准产生固定长度帧的电路设置在每个节点中，以便采用独立的时钟系统，同步装置所需的公共同步时钟的分配由同时将同步时钟的转换点信息嵌入固定长度帧中的特定空间中。此外，每个节点产生具有独立时钟信号的固定长度传输帧，另一方面，从应用于网络的信息量变为恒定的要求，在每个节点中提供用于提取接收时钟的电路用于临时存储接收到的信息的存储装置，以及信息输出量控制电路，当存储在存储装置中的信息量变得超过预定的第一参考值和信息量时，在一帧中发送的信息量增加当存储在存储装置中的信息量变得小于预定的第二参考值时，在一帧中发送的信息量减少。

34. 发明授权

US5197097A Cell signal processing circuit and optical switch apparatus using the same 失效
标题翻译：使用该单元的信号信号处理电路和光开关装置
公开(公告)号：US5197097A
公开(公告)日：1993-03-23
申请号：US638577
申请日：1991-01-07
申请人： Yasushi Takahashi , Eiichi Amada , Kimiaki Ando , Masanori Miyata
发明人： Yasushi Takahashi , Eiichi Amada , Kimiaki Ando , Masanori Miyata
IPC分类号： H04B10/27 , H04B10/00 , H04J3/06 , H04L12/70 , H04L12/931 , H04Q3/52 , H04Q11/00 , H04Q11/04
CPC分类号： H04Q11/04 , H04J3/0605 , H04Q11/0001 , H04Q11/0066
摘要： A cell signal processing circuit is provided which is capable of precisely extracting a timing signal and a cell synchronizing signal. The cell signal processing circuit is principally composed of a signal adder circuit for adding a dummy signal comprising bit signals in a direct current balanced state to an end portion of respective inputted time series cell signals, and a separator circuit for separating and outputting the time series cell signals. Each dummy signal being composed of the same number of bits "0" and "1" is added to input signals in the form of time series cells such that signal cells are exchanged at a time of a bit "0" in the dummy signal. An optical switch apparatus using the cell signal processing circuit as an optical switch array is also provided which includes a photoelectric converter for converting the time series optical cell signal to an electric signal, a clock recovery circuit for extracting a clock signal from an output from the photoelectric converter, a cell synchronization circuit for extracting a cell synchronizing signal from the output from the photoelectric converter, and a decision circuit for deciding between signals in the output from the photoelectric converter by the use of the clock signal. The optical switch apparatus of the invention is simple and is not influenced by data loss and jitter.

35. 发明授权

US5113392A Communication apparatus for reassembling packets received from network into message 失效
标题翻译：将从网络接收的分组重新传送到消息的通信装置
公开(公告)号：US5113392A
公开(公告)日：1992-05-12
申请号：US539961
申请日：1990-06-18
申请人： Yoshihiro Takiyasu , Mitsuhiro Yamaga , Kazunori Nakamura , Eiichi Amada , Hidehiko Jusa , Naoya Kobayashi , Osamu Takada , Satoru Hirayama , Tatsuhito Iiyama
发明人： Yoshihiro Takiyasu , Mitsuhiro Yamaga , Kazunori Nakamura , Eiichi Amada , Hidehiko Jusa , Naoya Kobayashi , Osamu Takada , Satoru Hirayama , Tatsuhito Iiyama
IPC分类号： H04L13/08 , H04L12/813 , H04L12/815 , H04L12/863 , H04L12/951
CPC分类号： H04L49/3009 , H04L49/252
摘要： In a network having a plurality of node apparatus connected to a transmission line, each node apparatus segmenting a transmission message into information blocks of a predetermined length and transmitting them to the transmission line in the form of a fixed length packet (cell) having a source address, each node apparatus sequentially stores packets having different source addresses in vacant memory blocks of a buffer memory. There is written in each memory block the packet data as well as a next address pointer indicating a memory block in which the next received packet having the same source address is stored. When a packet containing the last information block of a message is received, stored in a read address queue is the address indicating the memory block which stores the first information block of the same packet. Reading the first block of a message from the buffer memory is executed in accordance with an address read from the read address queue, and reading the following blocks is executed in accordance with the next address pointer. Read/write of the buffer memory is alternately executed in units of memory block.

36. 发明授权

US5103447A High-speed ring LAN system 失效
标题翻译：高速环网系统
公开(公告)号：US5103447A
公开(公告)日：1992-04-07
申请号：US399901
申请日：1989-08-29
申请人： Yoshihiro Takiyasu , Toshiki Tanaka , Taihei Suzuki , Eiichi Amada , Yukiji Yamauchi , Mitsuhiro Yamaga , Matsuaki Terada , Kunio Hiyama
发明人： Yoshihiro Takiyasu , Toshiki Tanaka , Taihei Suzuki , Eiichi Amada , Yukiji Yamauchi , Mitsuhiro Yamaga , Matsuaki Terada , Kunio Hiyama
IPC分类号： H04J3/08 , H04J3/16 , H04L12/43 , H04L12/56 , H04Q11/04
CPC分类号： H04J3/08 , H04J3/1617 , H04L12/43 , H04Q11/0478 , H04J2203/0042 , H04J2203/0089 , H04L2012/5652 , H04L2012/5672
摘要： A high-speed ring LAN capable of accommodating at least one public network having a signal transmission rate of 155.57 MHz, and at least one sub-LAN having a signal transmission rate of 100 MHz. The high-speed LAN has a signal transmission rate of 155.52 Mbps.times.n (n is an even number). SONET (Synchronous Optical NETwork) subframes each comprising a 9 bytes.times.9 section overhead area and a 261 bytes.times.9 virtual container 4 (VC-4) area flow in a time-divisional n-multiplexed format. The respective node devices inserted in the transmission path have one or more ports to accommodate sub-LANs or public networks. Information is exchanged in units of a fixed-length packet between a received SONET subframe and an asynchronous packet whereas information is exchanged in units of a byte between the SONET subframe and a synchronous port.
摘要翻译：能够容纳具有155.57MHz的信号传输速率的至少一个公共网络的高速环形LAN以及信号传输速率为100MHz的至少一个子LAN。高速LAN的信号传输速率为155.52Mbps×n（n为偶数）。 SONET（同步光网络）子帧，每个子帧包括时分多路复用格式的9字节×9部分开销区域和261字节×9虚拟容器4（VC-4）区域流。插入传输路径中的各个节点设备具有一个或多个端口以适应子LAN或公共网络。在接收的SONET子帧和异步分组之间以固定长度的分组为单位交换信息，而以SONET子帧和同步端口之间的字节为单位交换信息。

37. 发明授权

US4841521A Method and system for bidirectionally transmitting data 失效
标题翻译：双向传输数据的方法和系统
公开(公告)号：US4841521A
公开(公告)日：1989-06-20
申请号：US55036
申请日：1987-05-28
申请人： Eiichi Amada , Hirotoshi Shirasu , Hiroshi Takatori , Tohru Kazawa , Toshiro Suzuki , Takanori Miyamoto , Tatsuya Kameyama
发明人： Eiichi Amada , Hirotoshi Shirasu , Hiroshi Takatori , Tohru Kazawa , Toshiro Suzuki , Takanori Miyamoto , Tatsuya Kameyama
IPC分类号： H04L5/14
CPC分类号： H04L5/1484
摘要： A method and a system for bidirectional transmission/reception of data between two terminal stations, in which each transmission period is divided into a plurality of first time sections for relatively low speed data transmission and at least one second time section for relatively high speed data transmission, the direction of transmission between the terminal stations being predetermined in each of the first time sections, while the direction of transmission between the terminal stations is reversible in each of the second time sections, each second time section being preceded by one of the first time sections. Transmission of information data and control data is performed from one to the other terminal station in a predetermined direction in each first time section, and the direction of data transmission between the terminal stations in the next second time section is determined on the basis of control data contained in the relatively low speed data transmission.
摘要翻译：一种用于在两个终端站之间双向传输/接收数据的方法和系统，其中每个传输周期被分成用于相对低速数据传输的多个第一时间段和用于相对高速数据传输的至少一个第二时间段所述终端站之间的传输方向在所述第一时间段中的每一个中是预定的，而在所述第二时间段中的每一个中，所述终端站之间的传输方向是可逆的，每个第二时间段之前是所述第一时间段之一部分。在每个第一时间段中，以预定方向从一个终端站到另一个终端站发送信息数据和控制数据，并且基于控制数据确定下一个第二时间段中的终端站之间的数据传输方向包含在相对低速的数据传输中。

38. 发明授权

US4608464A Interface circuit interconnecting a bidirectional two-wire line with unidirectional four-wire lines 失效
标题翻译：接口电路将双向双线线路与单向四线制线路互连
公开(公告)号：US4608464A
公开(公告)日：1986-08-26
申请号：US605904
申请日：1984-05-01
申请人： Yuichi Morikawa , Hirohiko Sato , Eiichi Amada , Toshiro Suzuki , Hirotoshi Shirasu , Hiroshi Kuwahara
发明人： Yuichi Morikawa , Hirohiko Sato , Eiichi Amada , Toshiro Suzuki , Hirotoshi Shirasu , Hiroshi Kuwahara
IPC分类号： H04B3/03 , H04B3/20 , H04B3/23 , H04B1/58
CPC分类号： H04B3/03 , H04B3/23
摘要： In an interface circuit which couples a two-wire line of bidirectional transmission and unidirectional four-wire receiving and transmitting lines; in order to permit the interface circuit to operate in adaptation to the fluctuation of an impedance with the two-wire line side viewed from the four-wire receiving line, the four-wire receiving line is provided with a plurality of filters and a group of switches for selecting the filters, an output of the four-wire transmitting line is compared with outputs obtained by scanning the filters, and the filter providing the minimum output difference in the comparisons is selected and connected.
摘要翻译：在耦合双向传输双线线路和单向四线接收和发射线路的接口电路中; 为了允许接口电路适应于从四线接收线观察到的双线线路的阻抗的波动，四线接收线路设置有多个滤波器和一组用于选择滤波器的开关，将四线传输线的输出与通过扫描滤波器获得的输出进行比较，并选择并连接提供比较中最小输出差的滤波器。

39. 发明授权

US4543652A Time-division switching unit 失效
标题翻译：时分切换单元
公开(公告)号：US4543652A
公开(公告)日：1985-09-24
申请号：US517697
申请日：1983-07-27
申请人： Eiichi Amada , Hiroshi Kuwahara , Hirotoshi Shirasu , Taihei Suzuki , Takashi Morita
发明人： Eiichi Amada , Hiroshi Kuwahara , Hirotoshi Shirasu , Taihei Suzuki , Takashi Morita
IPC分类号： H04J3/06 , H04Q11/04
CPC分类号： H04J3/0629 , H04Q11/04
摘要： A time-division switching unit for connecting a desired channel of a desired one of a plurality of input highways to a desired channel of a desired one of a plurality of output highways is disclosed. A frame synchronization circuit of the time-division switching unit variably delays signals of the input highways within one channel period, writes the signals to a speech memory for each channel, modifies write addresses to the speech memory to attain frame synchronization, extracts frame synchronization signals of the respective highways from the input and output of the speech memory, and controls the amount of delay within one channel period and the amount of address modification by the extracted synchronization signals.
摘要翻译：公开了一种时分切换单元，用于将多个输入高速公路中期望的一个输入高速公路的期望频道连接到多个输出高速公路中期望的一个输出高速公路的期望频道。时分切换单元的帧同步电路在一个信道周期内可变地延迟输入高速公路的信号，将信号写入每个信道的语音存储器，将写入地址修改为语音存储器以获得帧同步，提取帧同步信号从控制语音存储器的输入和输出的各个高速公路，并且控制一个信道周期内的延迟量以及所提取的同步信号的地址修改量。

40. 发明授权

US4223389A Recursive digital filter having means to prevent overflow oscillation 失效
标题翻译：递归数字滤波器具有防止溢出振荡的装置
公开(公告)号：US4223389A
公开(公告)日：1980-09-16
申请号：US909066
申请日：1978-05-24
申请人： Eiichi Amada , Makoto Ohnishi
发明人： Eiichi Amada , Makoto Ohnishi
IPC分类号： E04G1/22 , H03H17/04 , G06F15/34 , G06F7/38
CPC分类号： H03H17/0461 , H03H17/0405
摘要： This invention has been made in order to prevent the malfunction due to an overflow, of a combinatorial type recursive digital filter whose feedback side is of the second or higher order. Means for detecting the overflow of the output of an arithmetic unit which executes an addition within the filter is additionally provided, and when the overflow has developed, the contents of shift registers for delay on, at least, the feedback side are reset by an output from the detecting means.
摘要翻译：本发明是为了防止由于溢出而引起的反馈侧为二阶以上的组合型递归数字滤波器的故障。附加地提供用于检测在滤波器内执行相加的运算单元的输出的溢出的装置，并且当溢出发展时，至少在反馈侧的延迟的移位寄存器的内容被输出从检测装置。

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