专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4841521A Method and system for bidirectionally transmitting data 失效
标题翻译：双向传输数据的方法和系统
公开(公告)号：US4841521A
公开(公告)日：1989-06-20
申请号：US55036
申请日：1987-05-28
申请人： Eiichi Amada , Hirotoshi Shirasu , Hiroshi Takatori , Tohru Kazawa , Toshiro Suzuki , Takanori Miyamoto , Tatsuya Kameyama
发明人： Eiichi Amada , Hirotoshi Shirasu , Hiroshi Takatori , Tohru Kazawa , Toshiro Suzuki , Takanori Miyamoto , Tatsuya Kameyama
IPC分类号： H04L5/14
CPC分类号： H04L5/1484
摘要： A method and a system for bidirectional transmission/reception of data between two terminal stations, in which each transmission period is divided into a plurality of first time sections for relatively low speed data transmission and at least one second time section for relatively high speed data transmission, the direction of transmission between the terminal stations being predetermined in each of the first time sections, while the direction of transmission between the terminal stations is reversible in each of the second time sections, each second time section being preceded by one of the first time sections. Transmission of information data and control data is performed from one to the other terminal station in a predetermined direction in each first time section, and the direction of data transmission between the terminal stations in the next second time section is determined on the basis of control data contained in the relatively low speed data transmission.
摘要翻译：一种用于在两个终端站之间双向传输/接收数据的方法和系统，其中每个传输周期被分成用于相对低速数据传输的多个第一时间段和用于相对高速数据传输的至少一个第二时间段所述终端站之间的传输方向在所述第一时间段中的每一个中是预定的，而在所述第二时间段中的每一个中，所述终端站之间的传输方向是可逆的，每个第二时间段之前是所述第一时间段之一部分。在每个第一时间段中，以预定方向从一个终端站到另一个终端站发送信息数据和控制数据，并且基于控制数据确定下一个第二时间段中的终端站之间的数据传输方向包含在相对低速的数据传输中。

2. 发明授权

US4775989A Timing phase detector circuit 失效
标题翻译：定时相位检测电路
公开(公告)号：US4775989A
公开(公告)日：1988-10-04
申请号：US878582
申请日：1986-06-26
申请人： Hiroshi Takatori , Toshiro Suzuki , Tatsuya Kameyama
发明人： Hiroshi Takatori , Toshiro Suzuki , Tatsuya Kameyama
IPC分类号： H04L7/027 , H04L7/00 , H04L7/02 , H04L7/033 , H04L7/04 , H04L7/08
CPC分类号： H04L7/0331 , H04L7/0066 , H04L7/041
摘要： In a waveform differential type timing phase detector circuit, phase information available from the timing phase detector circuit is made valid for use as control information only when the input pulse assumes a specified pattern, in order to detect a timing phase signal removal of jitters due to waveform distortion.
摘要翻译：在波形差分型定时相位检测器电路中，只有当输入脉冲采用指定模式时，才能从定时相位检测器电路获得的相位信息用作控制信息，以便检测定时相位信号消除由于波形失真。

3. 发明授权

US4687998A Pulse width generating circuit synchronized with clock signal and corresponding to a reference voltage 失效
公开(公告)号：US4687998A
公开(公告)日：1989-08-18
申请号：US759865
申请日：1985-07-29
申请人： Hiroshi Takatori , Toshiro Suzuki , Osamu Matsubara , Izuru Yamada
发明人： Hiroshi Takatori , Toshiro Suzuki , Osamu Matsubara , Izuru Yamada
IPC分类号： H03K4/02 , H03K5/04 , H03K5/22 , H03K5/159 , H03K5/00
CPC分类号： H03K4/023
摘要： A pulse generating circuit is provided for generating a pulse having a time width synchronized with an input pulse and corresponding to a reference voltage. The circuit is particularly designed not to be affected by parasitic capacitance. A circuit for charging one electrode of an integrating circuit with a constant current is controlled by turning on or off a switch in response to the input pulse. The other electrode of the integrating capacitor is connected with a reference voltage source by driving a switch in response to a pulse having a pulse width which contains the time period of the input pulse and which is wider than the input pulse. A comparator is provided for comparing the potential at one electrode of the integrating capacitor and ground potential. A desired pulse is generated by a logic circuit which is receives both the output of the comparator and the input pulse.

4. 发明授权

US4769612A Integrated switched-capacitor filter with improved frequency characteristics 失效
标题翻译：具有改进频率特性的集成开关电容滤波器
公开(公告)号：US4769612A
公开(公告)日：1988-09-06
申请号：US110574
申请日：1987-10-15
申请人： Masashi Tamakoshi , Toshiro Suzuki , Hiroshi Takatori
发明人： Masashi Tamakoshi , Toshiro Suzuki , Hiroshi Takatori
IPC分类号： H03H19/00 , H03K5/00
CPC分类号： H03H19/004
摘要： A switched-capacitor filter constituted in the form of a semiconductor integrated circuit has an input circuit which consists of at least one noninversion-type switched-capacitor and at least two inversion-type switched-capacitors that are connected in parallel with each other. The two inversion-type switched-capacitors have different writing timings and reading timings relative to each other. With this setup, capacitances of the switched-capacitors need not be extremely increased even when it is desired to maintain a zero-point frequency of the filter at a very low value. Further, there is no need of providing a circuit such as sample holding circuit which requires extra area and consumes additional electric power.
摘要翻译：以半导体集成电路的形式构成的开关电容滤波器具有输入电路，其由至少一个非反相型开关电容器和至少两个彼此并联连接的反相型开关电容器组成。两个反相型开关电容器具有不同的写入定时和相对于彼此的读取定时。通过这种设置，即使希望将滤波器的零点频率保持在非常低的值，开关电容器的电容也不需要极大地增加。此外，不需要提供诸如需要额外面积并消耗额外电力的样品保持电路的电路。

5. 发明授权

US4658217A Timing signal extracting circuit 失效
标题翻译：定时信号提取电路
公开(公告)号：US4658217A
公开(公告)日：1987-04-14
申请号：US654897
申请日：1984-09-27
申请人： Hiroshi Takatori , Toshiro Suzuki , Keiji Tomooka
发明人： Hiroshi Takatori , Toshiro Suzuki , Keiji Tomooka
IPC分类号： H04L7/00 , H04L7/02 , H04L7/027 , H04L7/033 , H03B1/00 , H03K5/13 , H03L7/00
CPC分类号： H04L7/0054 , H04L7/027
摘要： A timing signal extraction circuit has a clock signal extractor for extracting from a transmitted data signal a clock component synchronous with the transmission rate of the transmitted signal, an oscillator having an oscillation frequency about M (M: an integer) times as high as the transmission rate of the transmitted signal, a phase-locked loop detecting the phase difference between the output signal of a frequency divider frequency-dividing the output signal of the oscillator and the output signal of the clock signal extractor thereby controlling the operating phase of the oscillator, and a logic circuit producing a plurality of pulse trains whose bit rate is equal to the transmission rate of the transmitted signal and which have respectively different phases. A pulse train having a desired phase is selected from among the plural pulse trains to provide a decision timing signal.
摘要翻译：定时信号提取电路具有时钟信号提取器，用于从发送的数据信号中提取与发送信号的传输速率同步的时钟分量，振荡器的振荡频率大约为传输的M（M：整数）倍发送信号的速率，锁相环检测分频振荡器的输出信号的分频器的输出信号与时钟信号提取器的输出信号之间的相位差，从而控制振荡器的工作相位，以及产生多个脉冲串的逻辑电路，其比特率等于发送信号的传输速率，并且具有分别不同的相位。从多个脉冲串中选择具有期望相位的脉冲串，以提供判定定时信号。

6. 发明授权

US4835482A Semiconductor integrated circuit forming a switched capacitor filter 失效
标题翻译：形成开关电容滤波器的半导体集成电路
公开(公告)号：US4835482A
公开(公告)日：1989-05-30
申请号：US233012
申请日：1988-08-17
申请人： Masashi Tamakoshi , Toshiro Suzuki , Hiroshi Takatori
发明人： Masashi Tamakoshi , Toshiro Suzuki , Hiroshi Takatori
IPC分类号： H03H19/00
CPC分类号： H03H19/004
摘要： A switched-capacitor filter of the present invention constituted in the form of a semiconductor integrated circuit has an input circuit which consists of at least one noninversion-type switched-capacitor and at least two inversion-type switched-capacitors that are connected in parallel with each other. The two inversion-type switched-capacitors have different writing timings and reading timings relative to each other. With this setup, capacitances of the switched-capacitors need not be extremely increased even when it is desired to maintain a zero-point frequency of the filter at a very low value. Further, there is no need of providing a circuit such as sample holding circuit which requires extra area and consumes additional electric power.
摘要翻译：以半导体集成电路的形式构成的本发明的开关电容滤波器具有输入电路，该输入电路由至少一个非反相型开关电容器和至少两个反相型开关电容器组成，所述至少两个反相型开关电容器与彼此。两个反相型开关电容器具有不同的写入定时和相对于彼此的读取定时。通过这种设置，即使希望将滤波器的零点频率保持在非常低的值，开关电容器的电容也不需要极大地增加。此外，不需要提供诸如需要额外面积并消耗额外电力的样品保持电路的电路。

7. 发明授权

US4500999A Line equalizer 失效
标题翻译：线均衡器
公开(公告)号：US4500999A
公开(公告)日：1985-02-19
申请号：US444227
申请日：1982-11-24
申请人： Hiroshi Takatori , Toshiro Suzuki
发明人： Hiroshi Takatori , Toshiro Suzuki
IPC分类号： H03H15/00 , H04B3/06 , H04B3/14
CPC分类号： H04B3/145
摘要： A line equalizer including a .sqroot.f equalizer for compensating a .sqroot.f-characteristic of a transmission line, a BT equalizer connected in series with the .sqroot.f equalizer for removing an echo component caused by a bridged tap (namely, BT) on the transmission line, and a circuit for controlling the .sqroot.f equalizer is disclosed. A signal applied to the .sqroot.f equalizer is subjected to over-equalization to make the time domain length of impulse response at the output of the .sqroot.f equalizer small. The equalization state of the output of the .sqroot.f equalizer is judged by signals formed in the BT equalizer, and the gain of the .sqroot.f equalizer is controlled on the basis of the result of judgement. In this manner, the .sqroot.f equalizer is controlled without suffering any interference between a control loop of the .sqroot.f equalizer and a control loop of the BT equalizer.
摘要翻译：包括用于补偿传输线的2ROOT f特性的2ROOT f均衡器的线均衡器，与2ROOT f均衡器串联连接的BT均衡器，用于消除由传输线上的桥接抽头（即BT）引起的回波分量并且公开了用于控制2ROOT f均衡器的电路。施加到2ROOT f均衡器的信号经过过均衡，使得2ROOT f均衡器的输出端的脉冲响应的时域长度较小。通过在BT均衡器中形成的信号判断2ROOT f均衡器的输出的均衡状态，并根据判断结果控制2ROOT f均衡器的增益。以这种方式，可以控制2ROOT f均衡器，而不会在2ROOT f均衡器的控制回路和BT均衡器的控制回路之间产生任何干扰。

8. 发明授权

US4459698A Variable equalizer 失效
标题翻译：可变均衡器
公开(公告)号：US4459698A
公开(公告)日：1984-07-10
申请号：US358437
申请日：1982-03-15
申请人： Osamu Yumoto , Toshiro Suzuki , Hiroshi Takatori , Yoshitaka Takasaki
发明人： Osamu Yumoto , Toshiro Suzuki , Hiroshi Takatori , Yoshitaka Takasaki
IPC分类号： H03H7/01 , H03H19/00 , H04B3/06 , H04L25/03 , H04L25/04
CPC分类号： H04L25/03019
摘要： A small-sized LSI variable equalizer is provided for accurately equalizing waveforms of signals transmitted via transmission lines of different distances. Variable equalizer units capable of stepwise changing the equalizing characteristics thereof are connected in series with each other with the variable equalizer units having variable step widths different from each other. An output signal of the variable equalizer units is compared with a reference signal to convert the comparison output signal to a digital signal which includes an upper order bits and lower order bits, whereby one of the equalizer units which has a wide variable step width is controlled by the upper order bits and the other of the equalizer units which has a narrow variable step width is controlled by the lower order bits.
摘要翻译：提供小型LSI可变均衡器，用于精确地均衡通过不同距离的传输线传输的信号的波形。能够逐步改变其均衡特性的可变均衡器单元彼此串联连接，而可变均衡器单元具有彼此不同的可变步长。将可变均衡器单元的输出信号与参考信号进行比较，以将比较输出信号转换为包括高阶位和低位位的数字信号，由此控制具有宽可变步长的均衡器单元之一通过较低阶比特和具有窄可变步宽的均衡器单元中的另一个由较低阶比特来控制。

9. 发明授权

US08827491B2 Lighting device 有权
标题翻译：照明设备
公开(公告)号：US08827491B2
公开(公告)日：2014-09-09
申请号：US13809744
申请日：2011-07-13
申请人： Hiroshi Takatori , Akinobu Seki , Noriyuki Kawahara
发明人： Hiroshi Takatori , Akinobu Seki , Noriyuki Kawahara
IPC分类号： F21V7/00 , F21V5/04 , G02B3/08 , F21S2/00 , F21Y101/02
CPC分类号： F21V7/0083 , F21S2/005 , F21V5/04 , F21V7/0091 , F21Y2115/10 , G02B3/08
摘要： A lighting device preventing an illumination variation on a surface to be irradiated. The lighting device has a first light emitting surface section (102a) which is a surface formed by rotating a bus with a central axis as a rotation axis in a first angle area (−θ1≦θ≦θ1) of an angle (θ) relative to a cross section of the bus which is an intersection line with the cross section perpendicular to a surface (801a) to be irradiated and including the central axis of a lighting lens (100), a second light emitting surface section (102b) formed in a second angle area (θ1≦θ≦180° and −180°≦θ≦−θ1) of the angle (θ) so that a light flux emitted toward the surface (801a) increases as compared with the case where the first light emitting surface section (102a) is formed in a whole-angle area (0°≦θ
摘要翻译：一种防止被照射表面上的照明变化的照明装置。照明装置具有第一发光表面部分（102a），该第一发光表面部分（102a）是通过使第一角度区域（ - ＆lt;＆lt; 1＆nlE;＆thetas;＆nlE;＆amp; thetas; 1）中的旋转轴线的中心轴线的总线旋转而形成的表面相对于总线的横截面的角度（θ），其是与要照射的表面（801a）垂直的横截面的交点，并且包括照明透镜（100）的中心轴，第二发光表面部分（102b）形成在角度（θ）的第二角度区域（θ; 1＆nlE;＆amp;;;; n1E; 180°和-180°＆nlE;; thetas; 1）中，与第一发光面部（102a）形成在发光面部（102）上的全角度区域（0°＆lt; 1 |θ3; 360°）的情况相比，朝向表面（801a）由第一发光表面部分（102a）和第二发光表面部分（102a）之间的步骤形成的第三发光表面部分（102c） d发光面部（102b）。

10. 发明申请

US20120076195A1 SCALED SIGNAL PROCESSING ELEMENTS FOR REDUCED FILTER TAP NOISE 有权
标题翻译：用于减少滤波器噪声的缩放信号处理元件
公开(公告)号：US20120076195A1
公开(公告)日：2012-03-29
申请号：US13312273
申请日：2011-12-06
申请人： Mark Joseph Callicotte , Hiroshi Takatori
发明人： Mark Joseph Callicotte , Hiroshi Takatori
IPC分类号： H03H7/30
CPC分类号： H03H21/0067 , H03H21/0001 , H03H21/0012
摘要： An adaptive transversal filter having tap weights Wj which are products of corresponding tap coefficients Cj and tap gains Mj is provided. A filter control loop controls all of the tap coefficients Cj such that an error signal derived from the filter output is minimized. One or more tap control loops controls a tap gain Mk such that the corresponding tap coefficient Ck satisfies a predetermined control condition. For example, |Ck| can be maximized subject to a constraint |Ck| Cmax, where Cmax is a predetermined maximum coefficient value. In this manner, the effect of quantization noise on the coefficients Cj can be reduced. Multiple tap control loops can be employed, one for each tap. Alternatively, a single tap control loop can be used to control multiple taps by time interleaving.
摘要翻译：提供具有作为对应抽头系数Cj和抽头增益Mj的乘积的抽头权重Wj的自适应横向滤波器。滤波器控制环控制所有抽头系数Cj，使得从滤波器输出得到的误差信号最小化。一个或多个抽头控制回路控制抽头增益Mk使得对应的抽头系数Ck满足预定的控制条件。例如| Ck | 可以最大限度地受限于| Ck | Cmax，其中Cmax是预定的最大系数值。以这种方式，可以减小量化噪声对系数Cj的影响。可以采用多个抽头控制回路，每个抽头一个。或者，可以使用单抽头控制回路来通过时间交织来控制多个抽头。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式