专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5113392A Communication apparatus for reassembling packets received from network into message 失效
标题翻译：将从网络接收的分组重新传送到消息的通信装置
公开(公告)号：US5113392A
公开(公告)日：1992-05-12
申请号：US539961
申请日：1990-06-18
申请人： Yoshihiro Takiyasu , Mitsuhiro Yamaga , Kazunori Nakamura , Eiichi Amada , Hidehiko Jusa , Naoya Kobayashi , Osamu Takada , Satoru Hirayama , Tatsuhito Iiyama
发明人： Yoshihiro Takiyasu , Mitsuhiro Yamaga , Kazunori Nakamura , Eiichi Amada , Hidehiko Jusa , Naoya Kobayashi , Osamu Takada , Satoru Hirayama , Tatsuhito Iiyama
IPC分类号： H04L13/08 , H04L12/813 , H04L12/815 , H04L12/863 , H04L12/951
CPC分类号： H04L49/3009 , H04L49/252
摘要： In a network having a plurality of node apparatus connected to a transmission line, each node apparatus segmenting a transmission message into information blocks of a predetermined length and transmitting them to the transmission line in the form of a fixed length packet (cell) having a source address, each node apparatus sequentially stores packets having different source addresses in vacant memory blocks of a buffer memory. There is written in each memory block the packet data as well as a next address pointer indicating a memory block in which the next received packet having the same source address is stored. When a packet containing the last information block of a message is received, stored in a read address queue is the address indicating the memory block which stores the first information block of the same packet. Reading the first block of a message from the buffer memory is executed in accordance with an address read from the read address queue, and reading the following blocks is executed in accordance with the next address pointer. Read/write of the buffer memory is alternately executed in units of memory block.

2. 发明授权

US5220562A Bridge apparatus and a communication system between networks using the bridge apparatus 失效
标题翻译：桥接设备和使用桥接设备的网络之间的通信系统
公开(公告)号：US5220562A
公开(公告)日：1993-06-15
申请号：US520712
申请日：1990-05-08
申请人： Osamu Takada , Katsuyoshi Onishi , Koichi Kimura , Kazunori Nakamura , Yoshihiro Takiyasu , Mitsuhiro Yamaga , Kunio Hiyama
发明人： Osamu Takada , Katsuyoshi Onishi , Koichi Kimura , Kazunori Nakamura , Yoshihiro Takiyasu , Mitsuhiro Yamaga , Kunio Hiyama
IPC分类号： H04L12/46
CPC分类号： H04L12/4616 , H04L45/742
摘要： Frontend LANs connecting plural stations are connected to plural nodes of a backbone LAN respectively. The backbone LAN is constituted by plural physical or logical links, and each node corresponds to each frontend LAN. A first data block is segmented into one or plural second data block units of fixed length and transferred to destination nodes, a bridge is provided in order to assemble the second data blocks into the first data block. The bridge can transmit the second data blocks to arbitrary links, and the receiving is performed through one link. The bridge a decoder also has a decoder for decoding whether the learning should be performed or not, based on the learning indication information existing in the second data block including the routing information.

3. 发明授权

US5247518A High-speed ring lan system 失效
标题翻译：高速环网系统
公开(公告)号：US5247518A
公开(公告)日：1993-09-21
申请号：US819821
申请日：1992-01-13
申请人： Yoshihiro Takiyasu , Toshiki Tanaka , Taihei Suzuki , Eiichi Amada , Yukiji Yamauchi , Mitsuhiro Yamaga , Matsuaki Terada , Kunio Hiyama
发明人： Yoshihiro Takiyasu , Toshiki Tanaka , Taihei Suzuki , Eiichi Amada , Yukiji Yamauchi , Mitsuhiro Yamaga , Matsuaki Terada , Kunio Hiyama
IPC分类号： H04J3/08 , H04J3/16 , H04L12/43 , H04L12/56 , H04Q11/04
CPC分类号： H04Q11/0478 , H04J3/08 , H04J3/1617 , H04L12/43 , H04J2203/0042 , H04J2203/0089 , H04L2012/5652 , H04L2012/5672
摘要： A high-speed ring LAN capable of accommodating at least one public network having a signal transmission rate of 155.57 MHz, and at least one sub-LAN having a signal transmission rate of 100 MHz. The high-speed LAN has a signal transmission rate of 155.52 Mbps .times.n (n is an even number). SONET (Synchronous Optical NETwork) subframes each comprising a 9 bytes .times.9 section overhead area and a 261 bytes .times.9 virtual container 4 (VC-4) area flow in a time-divisional n-multiplexed format. The respective node devices inserted in the transmission path have one or more ports to accommodate sub-LANs or public networks. Information is exchanged in units of a fixed-length packet between a received SONET subframe and an asynchronous port whereas information is exchanged in units of a byte between the SONET subframe and a synchronous port.
摘要翻译：能够容纳具有155.57MHz的信号传输速率的至少一个公共网络的高速环形LAN以及信号传输速率为100MHz的至少一个子LAN。高速LAN的信号传输速率为155.52Mbps xn（n为偶数）。 SONET（同步光网络）子帧，每个子帧包括时分多路复用格式的9字节×9部分开销区域和261字节×9虚拟容器4（VC-4）区域流。插入传输路径中的各个节点设备具有一个或多个端口以适应子LAN或公共网络。信息以接收的SONET子帧和异步端口之间的固定长度分组为单位进行交换，而以SONET子帧和同步端口之间的字节为单位交换信息。

4. 发明授权

US5103447A High-speed ring LAN system 失效
标题翻译：高速环网系统
公开(公告)号：US5103447A
公开(公告)日：1992-04-07
申请号：US399901
申请日：1989-08-29
申请人： Yoshihiro Takiyasu , Toshiki Tanaka , Taihei Suzuki , Eiichi Amada , Yukiji Yamauchi , Mitsuhiro Yamaga , Matsuaki Terada , Kunio Hiyama
发明人： Yoshihiro Takiyasu , Toshiki Tanaka , Taihei Suzuki , Eiichi Amada , Yukiji Yamauchi , Mitsuhiro Yamaga , Matsuaki Terada , Kunio Hiyama
IPC分类号： H04J3/08 , H04J3/16 , H04L12/43 , H04L12/56 , H04Q11/04
CPC分类号： H04J3/08 , H04J3/1617 , H04L12/43 , H04Q11/0478 , H04J2203/0042 , H04J2203/0089 , H04L2012/5652 , H04L2012/5672
摘要： A high-speed ring LAN capable of accommodating at least one public network having a signal transmission rate of 155.57 MHz, and at least one sub-LAN having a signal transmission rate of 100 MHz. The high-speed LAN has a signal transmission rate of 155.52 Mbps.times.n (n is an even number). SONET (Synchronous Optical NETwork) subframes each comprising a 9 bytes.times.9 section overhead area and a 261 bytes.times.9 virtual container 4 (VC-4) area flow in a time-divisional n-multiplexed format. The respective node devices inserted in the transmission path have one or more ports to accommodate sub-LANs or public networks. Information is exchanged in units of a fixed-length packet between a received SONET subframe and an asynchronous packet whereas information is exchanged in units of a byte between the SONET subframe and a synchronous port.
摘要翻译：能够容纳具有155.57MHz的信号传输速率的至少一个公共网络的高速环形LAN以及信号传输速率为100MHz的至少一个子LAN。高速LAN的信号传输速率为155.52Mbps×n（n为偶数）。 SONET（同步光网络）子帧，每个子帧包括时分多路复用格式的9字节×9部分开销区域和261字节×9虚拟容器4（VC-4）区域流。插入传输路径中的各个节点设备具有一个或多个端口以适应子LAN或公共网络。在接收的SONET子帧和异步分组之间以固定长度的分组为单位交换信息，而以SONET子帧和同步端口之间的字节为单位交换信息。

5. 发明授权

US4759015A Ring network system for transmission of multicast information 失效
标题翻译：环网系统传输组播信息
公开(公告)号：US4759015A
公开(公告)日：1988-07-19
申请号：US911793
申请日：1986-09-26
申请人： Atsushi Takai , Kazunori Nakamura , Yoshihiro Takiyasu , Nagatoshi Usami , Mitsuhiro Yamaga
发明人： Atsushi Takai , Kazunori Nakamura , Yoshihiro Takiyasu , Nagatoshi Usami , Mitsuhiro Yamaga
IPC分类号： H04L12/18 , H04L12/433 , H04J3/00 , H04J3/16
CPC分类号： H04L12/1868 , H04L12/433
摘要： In a network system wherein a plurality of terminal devices communicates with each other via respective node devices over a ring transmission line, a transmitting node device can confirm whether a multicast information transmission has succeeded or failed. The transmitting node device send a response frame after a multicast information frame. A receiving node device relays the multicast information frame and a response frame from the upstream node device to the downstream one when the multicast information has been received successfully, or in case of a failure in receiving the multicast information, sends a response frame to the downstream node device by changing at least part of the response frame from the upstream node device. The transmitting node device can determine from a received response frame if there is one or more of the receiving node devices which cannot receive the multicast information.
摘要翻译：在多个终端设备经由环形传输线路经由各个节点设备进行通信的网络系统中，发送节点设备可以确认多播信息传输是否成功或失败。发送节点设备在组播信息帧之后发送响应帧。当接收到的组播信息成功接收时，接收节点设备将组播信息帧和上游节点设备的响应帧中继到下游节点，否则在接收到组播信息失败的情况下，向下游发送响应帧通过从上游节点设备改变响应帧的至少一部分来实现节点设备。发送节点设备可以从接收的响应帧确定是否存在不能接收多播信息的一个或多个接收节点设备。

6. 发明授权

US5224096A Frame strip method and apparatus therefor 失效
标题翻译：框架方法及其设备
公开(公告)号：US5224096A
公开(公告)日：1993-06-29
申请号：US583506
申请日：1990-09-17
申请人： Katsuyoshi Onishi , Koichi Kimura , Mitsuhiro Yamaga , Osamu Takada , Masahito Sasaki
发明人： Katsuyoshi Onishi , Koichi Kimura , Mitsuhiro Yamaga , Osamu Takada , Masahito Sasaki
IPC分类号： H04L12/433
CPC分类号： H04L12/433
摘要： A frame strip method for a bridge circuit for transparently forwarding data between a plurality of LANs (Local Area Network) without frame infinite circulation. The numbers of transmission/receive frames are counted. In counting the number, the validity/invalidity of a transmission frame is judged in accordance with the kind of the transmission frame. The validity/invalidity and strip/receive of a receive frame are judged in accordance with the kind of the receive frame. In accordance with the numbers of valid transmission/receive frames, a receive frame is stripped from the transmission line if the condition of (transmission frame number)>(receive frame number) is met.

7. 发明授权

US5210748A Address filter unit for carrying out address filter processing among plurality of networks and method thereof 失效
标题翻译：用于在多个网络中进行地址滤波处理的地址滤波器单元及其方法
公开(公告)号：US5210748A
公开(公告)日：1993-05-11
申请号：US652044
申请日：1991-02-04
申请人： Katsuyoshi Onishi , Osamu Takada , Koichi Kimura , Mitsuhiro Yamaga , Toshihiko Ogura , Yasushi Shibata
发明人： Katsuyoshi Onishi , Osamu Takada , Koichi Kimura , Mitsuhiro Yamaga , Toshihiko Ogura , Yasushi Shibata
IPC分类号： H04L12/46
CPC分类号： H04L45/742 , H04L12/4625
摘要： The present invention relates to an address filter method and unit to be used in a bridge unit or the like for connecting networks. The address filter unit carries out an address filter processing between a plurality of networks by using address information extracted from an incoming information frame registered in an entry table. In order to improve the processing efficiency of the address filter processing, the address filter unit includes timers corresponding to each address information registration, timer updating means for sequentially and intermittently advancing each timer value, and means for deleting registration of the address information corresponding to the timers from the entry table when a timer value becomes equal to or above a predetermined value. Further, the address filtering method includes a first step for sequentially generating, as an address of the entry table, a function (fi(a), i=1 to n) of a source address extracted from an incoming information frame at the time of a registration in the entry table or a destination address (a) extracted from an incoming information frame at the time of a retrieval from the entry table, a second step for deciding whether or not address information can be registered in an address generated in the first step in the entry table, at the time of registration, and a third step for deciding whether or not address information registered in an address generated in the first step in the entry table is desired address information, at the time of retrieval.
摘要翻译：本发明涉及用于连接网络的桥接单元等中使用的地址过滤方法和单元。地址过滤器单元通过使用从入口表中登记的输入信息帧提取的地址信息，在多个网络之间执行地址过滤处理。为了提高地址滤波处理的处理效率，地址滤波器单元包括与每个地址信息登记对应的定时器，用于顺序地和间歇地提前每个定时器值的定时器更新装置，以及用于删除对应于当定时器值变得等于或高于预定值时，来自输入表的定时器。此外，地址过滤方法包括：第一步骤，用于顺序地生成作为入口表的地址的从进入信息帧中提取的源地址的函数（fi（a），i = 1至n）在从入口表检索时从输入信息帧提取的入口表中的登记或目的地地址（a），用于判定地址信息是否可以登记在第一在注册时，在步骤中，在检索时，判定在入口表中的第一步骤中生成的地址中登记的地址信息是否为期望地址信息的第三步骤。

8. 发明授权

US4675884A Decoding circuit 失效
标题翻译：解码电路
公开(公告)号：US4675884A
公开(公告)日：1987-06-23
申请号：US812921
申请日：1985-12-23
申请人： Kazunori Nakamura , Mitsuhiro Yamaga , Ryozo Yoshino , Norihiko Sugimoto
发明人： Kazunori Nakamura , Mitsuhiro Yamaga , Ryozo Yoshino , Norihiko Sugimoto
IPC分类号： H03M3/04 , H03M5/12 , H04L25/48 , H04L27/22
CPC分类号： H03M5/12
摘要： A decoding circuit is operative to decode a differential Manchester code consisting of four symbols "J", "K", "1" and "0" each composed of two consecutive signal elements. For detection of the symbol "J" and consequent determination of the symbol boundary, the decoding circuit has a circuit configuration which takes advantage of the fact that the symbol "K" immediately follows the symbol "J" and three consecutive signal elements, two of which are included in the symbol "J" and one of which is for a symbol immediately preceding the symbol "J", have the same polarity. To prevent an error that a second occurrence of the symbol "J" is detected after completion of detection of the symbol "J", the decoding circuit has an additional circuit configuration which inhibits the detection of the symbol "J" until the symbol "0" or the symbol "1", for example, is detected.
摘要翻译：解码电路用于对由每个由两个连续的信号元素组成的四个符号“J”，“K”，“1”和“0”组成的差分曼彻斯特码进行解码。为了检测符号“J”并随后确定符号边界，解码电路具有利用符号“K”紧跟在符号“J”之后的事实的电路结构，以及三个连续的信号元素它们包括在符号“J”中，其中一个用于紧邻符号“J”之前的符号，具有相同的极性。为了防止在完成符号“J”的检测之后检测到符号“J”的第二次发生的错误，解码电路具有禁止符号“J”的检测直到符号“0”的附加电路配置 “或例如符号”1“。

9. 发明授权

US4899142A Ring network system and configuration control method 失效
标题翻译：环网系统和配置控制方法
公开(公告)号：US4899142A
公开(公告)日：1990-02-06
申请号：US46031
申请日：1987-05-04
申请人： Susumu Nakayashiki , Jiro Kashio , Takeshi Harakawa , Yoshinori Bekki , Mitsuhiro Yamaga
发明人： Susumu Nakayashiki , Jiro Kashio , Takeshi Harakawa , Yoshinori Bekki , Mitsuhiro Yamaga
IPC分类号： H04L12/437
CPC分类号： H04L12/437
摘要： A ring network system in which a plurality of line concentrators each having terminal stations connected thereto through respective branch lines are interconnected through at least one ring transmission lines. Each line concentrator includes configuration control switches capable of disconnecting from the ring transmission line all the branch lines placed under control of the line concentrator while holding the ring transmission line in the state to allow communication. The branch line(s) disconnected from the ring transmission line form(s) a local ring through cooperation with an internal transmission line. The line concentrator detected abnormality of communication or the line concentrator to be set to the rest state can undergo internal diagnosis operation or continue to be in the rest state without disturbing the communication among other line concentrators. At activation of the line concentrators, any of them may be activated arbitrarily and independently from each other by again connecting the branch lines to the ring transmission lines.

10. 发明授权

US4847611A Ring configuration of line concentrators 失效
标题翻译：线路集线器的环形配置
公开(公告)号：US4847611A
公开(公告)日：1989-07-11
申请号：US86821
申请日：1987-08-19
申请人： Yoshinori Bekki , Hiroyuki Wada , Mitsuhiro Yamaga , Susumu Nakayashiki
发明人： Yoshinori Bekki , Hiroyuki Wada , Mitsuhiro Yamaga , Susumu Nakayashiki
IPC分类号： H04L12/42
CPC分类号： H04L12/42
摘要： In a ring communications system including a plurality of line concentrators that are connected in the form of a ring, the line concentrators are connected together via a main ring, and the terminal stations connected to the line concentrators are connected to the main ring via ring subsidiaries. The main ring and the ring subsidiaries are connected together via ring connection switches that so work as to connect or disconnect the main ring and the ring subsidiaries. The ring connection switch is so constructed as to maintain the connected condition even when the power source of the line concentrator is in the turned-off state.
摘要翻译：在包括以环形连接的多个集线器的环形通信系统中，线路集线器通过主环连接在一起，连接到集线器的终端站通过环形子系统连接到主环。主环和环形子公司通过环形连接开关连接在一起，用于连接或断开主环和环形子公司。环形连接开关被构造成即使当线路集电器的电源处于关断状态时也保持连接状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式