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1. 发明申请

US20050076073A1 Biquad digital filter operating at maximum efficiency 有权
标题翻译： Biquad数字滤波器以最高的效率运行
公开(公告)号：US20050076073A1
公开(公告)日：2005-04-07
申请号：US10651402
申请日：2003-08-29
申请人： Srikanth Gurrapu
发明人： Srikanth Gurrapu
IPC分类号： G06F17/10 , H03H17/04
CPC分类号： G06F7/5443 , H03H17/0405
摘要： An architecture for a biquad (70), second-order infinite impulse response (IIR) digital filter, that is capable of operating at maximum efficiency, is disclosed. The biquad (70) includes coefficient memory (50) and data memory (52), along with control circuitry (53) that loads values from these memories (50, 52) into a coefficient register (52) and a data register (54), respectively. A multiplier (55) multiplies the values in the coefficient register (52) and data register (54), with the resulting product being stored in a product register (58). An accumulator (59) adds successive product results to derive a new output value in each instance of the IIR filter. A shadow register (60) temporarily stores the output of the accumulator (59) from a previous instance, permitting this output to be stored in the data memory (52) at a later time in the sequence. This permits the order of operations in the second and successive biquads to be altered so that each successive biquad instance can start well before the previous result is derived; as a result, the multiplier (55) is fed with values each cycle, enabling maximum efficiency operation.
摘要翻译：公开了一种能够以最大效率运行的双二阶（70）二阶无限脉冲响应（IIR）数字滤波器的架构。二进制（70）包括系数存储器（50）和数据存储器（52）以及将这些存储器（50,52）中的值加载到系数寄存器（52）和数据寄存器（54）中的控制电路（53），分别。乘法器（55）将系数寄存器（52）和数据寄存器（54）中的值相乘，所得到的乘积存储在产品寄存器（58）中。累加器（59）添加连续的产品结果以在IIR滤波器的每个实例中导出新的输出值。影子寄存器（60）临时存储来自前一个实例的累加器（59）的输出，允许该序列在稍后的时间将该输出存储在数据存储器（52）中。这允许改变第二个和连续的二进制中的操作顺序，使得每个连续的二进制实例可以在导出先前的结果之前很好地开始; 结果，乘法器（55）每个周期被馈送值，从而实现最大效率的操作。

2. 发明授权

US4305133A Recursive type digital filter 失效
标题翻译：递归式数字滤波器
公开(公告)号：US4305133A
公开(公告)日：1981-12-08
申请号：US94915
申请日：1979-11-16
申请人： Eiichi Amada , Makoto Ohnishi , Hiroshi Kuwahara
发明人： Eiichi Amada , Makoto Ohnishi , Hiroshi Kuwahara
IPC分类号： H03H17/00 , H03H17/04 , G06F15/31 , G06F7/48
CPC分类号： H03H17/0405 , H03H17/0461
摘要： A recursive type digital filter receiving a digital input signal x(n) having a plurality of bits and delivering a ditial output signal y(n) satisfying the following equation, ##EQU1## where n indicates a natural number, M and N orders of time lag in the signal transference, a.sub.k and b.sub.k coefficients defined by a filter characteristic, a.sub.M and b.sub.N b being coefficients which are not equal to zero, comprises an output control circuit for delivering a digital signal indicating a positive or negative limit value in place of the digital output signal y(n) when the amplitude of the signal y(n) exceeds an allowable value. In combination with this output control circuit, the filter also utilizes a feedback signal for calculation purposes which feedback signal has its amplitude reduced from that of y(n) by a predetermined ratio. Further, an arrangement is provided for clearing registers of filter when necessary to prevent overflow oscillation.
摘要翻译：接收具有多个位的数字输入信号x（n）的递归型数字滤波器，并输出满足以下等式的初始输出信号y（n），其中n表示自然数，M和N个时间顺序信号传输滞后，由滤波器特性aM和bN b定义的ak和bk系数是不等于零的系数，包括输出控制电路，用于传送指示正或负极限值的数字信号代替数字输出信号y（n），当信号y（n）的振幅超过允许值时。与该输出控制电路相结合，滤波器还利用反馈信号进行计算，将反馈信号的幅度从y（n）的幅度减小预定比例。此外，为了防止溢出振荡，需要设置清除滤波器的寄存器的结构。

3. 发明申请

US20020118739A1 Digital filter and method for performing a multiplication based on a look-up table 失效
标题翻译：用于基于查找表执行乘法的数字滤波器和方法
公开(公告)号：US20020118739A1
公开(公告)日：2002-08-29
申请号：US09970757
申请日：2001-10-03
发明人： Thorsten Schier , Jonas Askeroth , Greger Sjoberg
IPC分类号： H03H007/40 , H03H007/30
CPC分类号： H03H17/0226 , H03H17/0405 , H03H17/0607
摘要： A digital and a multiplication method are described, which lead to an efficient architecture for hardware implementation of digital FIR and IIR filters into FPGAs. The multiplications of input sample data and delayed sample data with filter coefficients are performed by addressing look-up tables in which corresponding multiplication results are prestored. The size of the look-up tables is reduced by storing only those multiplication results which cannot be obtained by a shifting operation performed on the other pre-stored multiplication results, the input sample data, or the delayed sample data. Thereby, the size of the look-up tables can be compressed significantly such that an implementation of large digital filters into FPGAs is possible.
摘要翻译：描述了数字和乘法方法，其导致用于将FPGA和数字FIR滤波器硬件实现到FPGA中的有效架构。输入采样数据和具有滤波器系数的延迟采样数据的乘法通过寻址预置的相应乘法结果的查找表来执行。通过仅存储那些通过对其他预先存储的乘法结果，输入的采样数据或延迟的样本数据执行的移位操作而不能获得的相乘结果来减小查找表的大小。因此，可以显着地压缩查找表的大小，使得可以实现大型数字滤波器到FPGA中。

4. 发明授权

US4709343A Variable-passband variable-phase digital filter 失效
标题翻译：可变通带可变相位数字滤波器
公开(公告)号：US4709343A
公开(公告)日：1987-11-24
申请号：US687464
申请日：1984-12-28
申请人： Luc P. Van Cang
发明人： Luc P. Van Cang
IPC分类号： H03H17/02 , H03H17/04 , H03H17/06 , H03H17/08 , G06F15/31
CPC分类号： H03H17/0405 , H03H17/0294 , H03H17/0607 , H03H17/08
摘要： A variable-passband, variable-phase digital filter in which Q digital samples of a signal are entered through (Q-1) delay lines, to be delayed into q two-bit adjacent doublets. Weighting tables in read only memories are addressed by each doublet. Each weighting table includes the results of linear combinations of the weights of doublets composed of bits of the same order multiplied by multiplier coefficients which are smaller than unity. Each integral portion of a result found in a table is applied at the same time as the fractional portions of the other results provided by the other tables to the addressing inputs of a programmed memory containing binary words. Binary words are addressed in the prorammed memory by the integral and fractional portions of the results found in the weighting tables. Each binary word has a value equal to the linear combination of the corresponding values of the samples of the signal by the multiplier coefficients.
摘要翻译：通过（Q-1）延迟线输入信号的Q个数字采样的可变通带可变相位数字滤波器被延迟到q个两位相邻的双频。只读存储器中的加权表由每个双引号来处理。每个加权表包括由相同阶数的比特乘以小于1的乘数系数组成的双重权重的线性组合的结果。在表中找到的结果的每个积分部分与其他表格提供的其他结果的小数部分同时应用于包含二进制字的编程存储器的寻址输入。二进制字通过权重表中发现的结果的积分和分数部分在prorammed内存中进行寻址。每个二进制字具有等于由乘数系数的信号样本的对应值的线性组合的值。

5. 发明授权

US3822404A Digital filter for delta coded signals 失效
标题翻译：用于DELTA编码信号的数字滤波器
公开(公告)号：US3822404A
公开(公告)日：1974-07-02
申请号：US18997471
申请日：1971-10-18
申请人： IBM
发明人： CROISIER A , RISO V
IPC分类号： H03H17/04 , H04B7/00
CPC分类号： H03H17/0405 , H03H17/0411
摘要： A recursive digital filter comprising a digital accumulator for algebraically adding successive modified digital delta coded signals extracted from a memory medium, the memory medium storing said modified digital signals, the memory further being directly addressed by a predetermined number of digital signals fed back from the accumulator.
摘要翻译：一种递归数字滤波器，包括用于代数地添加从存储介质提取的连续修改的数字增量编码信号的数字累加器，所述存储介质存储所述修改的数字信号，所述存储器还通过从累加器反馈的预定数量的数字信号寻址。

6. 发明授权

US07159002B2 Biquad digital filter operating at maximum efficiency 有权
标题翻译： Biquad数字滤波器以最高的效率运行
公开(公告)号：US07159002B2
公开(公告)日：2007-01-02
申请号：US10651402
申请日：2003-08-29
申请人： Srikanth Gurrapu
发明人： Srikanth Gurrapu
IPC分类号： G06F17/10
CPC分类号： G06F7/5443 , H03H17/0405
摘要： An architecture for a biquad (70), second-order infinite impulse response (IIR) digital filter, that is capable of operating at maximum efficiency, is disclosed. The biquad (70) includes coefficient memory (50) and data memory (52), along with control circuitry (53) that loads values from these memories (50, 52) into a coefficient register (52) and a data register (54), respectively. A multiplier (55) multiplies the values in the coefficient register (52) and data register (54), with the resulting product being stored in a product register (58). An accumulator (59) adds successive product results to derive a new output value in each instance of the IIR filter. A shadow register (60) temporarily stores the output of the accumulator (59) from a previous instance, permitting this output to be stored in the data memory (52) at a later time in the sequence. This permits the order of operations in the second and successive biquads to be altered so that each successive biquad instance can start well before the previous result is derived; as a result, the multiplier (55) is fed with values each cycle, enabling maximum efficiency operation.
摘要翻译：公开了一种能够以最大效率运行的双二阶（70）二阶无限脉冲响应（IIR）数字滤波器的架构。二进制（70）包括系数存储器（50）和数据存储器（52）以及将这些存储器（50,52）中的值加载到系数寄存器（52）和数据寄存器（54）中的控制电路（53），分别。乘法器（55）将系数寄存器（52）和数据寄存器（54）中的值相乘，所得到的乘积存储在产品寄存器（58）中。累加器（59）添加连续的产品结果以在IIR滤波器的每个实例中导出新的输出值。影子寄存器（60）临时存储来自前一个实例的累加器（59）的输出，允许该序列在稍后的时间将该输出存储在数据存储器（52）中。这允许改变第二个和连续的二进制中的操作顺序，使得每个连续的二进制实例可以在导出先前的结果之前很好地开始; 结果，乘法器（55）每个周期被馈送值，从而实现最大效率的操作。

7. 发明授权

US4223389A Recursive digital filter having means to prevent overflow oscillation 失效
标题翻译：递归数字滤波器具有防止溢出振荡的装置
公开(公告)号：US4223389A
公开(公告)日：1980-09-16
申请号：US909066
申请日：1978-05-24
申请人： Eiichi Amada , Makoto Ohnishi
发明人： Eiichi Amada , Makoto Ohnishi
IPC分类号： E04G1/22 , H03H17/04 , G06F15/34 , G06F7/38
CPC分类号： H03H17/0461 , H03H17/0405
摘要： This invention has been made in order to prevent the malfunction due to an overflow, of a combinatorial type recursive digital filter whose feedback side is of the second or higher order. Means for detecting the overflow of the output of an arithmetic unit which executes an addition within the filter is additionally provided, and when the overflow has developed, the contents of shift registers for delay on, at least, the feedback side are reset by an output from the detecting means.
摘要翻译：本发明是为了防止由于溢出而引起的反馈侧为二阶以上的组合型递归数字滤波器的故障。附加地提供用于检测在滤波器内执行相加的运算单元的输出的溢出的装置，并且当溢出发展时，至少在反馈侧的延迟的移位寄存器的内容被输出从检测装置。

8. 发明授权

US4146931A Digital filter 失效
公开(公告)号：US4146931A
公开(公告)日：1979-03-27
申请号：US876597
申请日：1978-02-10
申请人： Jean-Marie Delforge
发明人： Jean-Marie Delforge
IPC分类号： H03H17/04 , G11C13/00
CPC分类号： H03H17/0405
摘要： A digital filter configuration incorporating read-only memories for coefficient storage is disclosed in which substantial reduction in memory requirements is achieved. Two read-only memories are addressed by only three arguments for a second-order filter or five arguments for a fourth-order filter.

9. 发明授权

US07046723B2 Digital filter and method for performing a multiplication based on a look-up table 失效
标题翻译：用于基于查找表执行乘法的数字滤波器和方法
公开(公告)号：US07046723B2
公开(公告)日：2006-05-16
申请号：US09970757
申请日：2001-10-03
申请人： Thorsten Schier , Jonas Askeroth , Greger Sjoberg
发明人： Thorsten Schier , Jonas Askeroth , Greger Sjoberg
IPC分类号： A03K5/159 , H03H7/30 , G06F15/00 , G06F17/14
CPC分类号： H03H17/0226 , H03H17/0405 , H03H17/0607
摘要： A digital and a multiplication method are described, which lead to an efficient architecture for a hardware implementation of digital FIR and IIR filters into FPGAs. The multiplications of input sample data and delayed sample data with filter coefficients are performed by addressing look-up tables in which corresponding multiplication results are prestored. The size of the look-up tables is reduced by storing only those multiplication results which cannot be obtained by a shifting operation performed on the other pre-stored multiplication results, the input sample data, or the delayed sample data. Thereby, the size of the look-up tables can be compressed significantly such that an implementation of large digital filters into FPGAs is possible.
摘要翻译：描述了数字和乘法方法，其导致用于将数字FIR和IIR滤波器硬件实现到FPGA中的有效架构。输入采样数据和具有滤波器系数的延迟采样数据的乘法通过寻址预置的相应乘法结果的查找表来执行。通过仅存储那些通过对其他预先存储的乘法结果，输入的采样数据或延迟的样本数据执行的移位操作而不能获得的相乘结果来减小查找表的大小。因此，可以显着地压缩查找表的大小，使得可以实现大型数字滤波器到FPGA中。

10. 发明授权

US4215415A Recursive digital filter comprising a circuit responsive to first sum and feedback sign bits and second sum sign and integer bits for detecting overflow in the second sum 失效
标题翻译：递归数字滤波器，包括响应于第一和和反馈符号位的电路，以及用于检测第二和中的溢出的第二和符号和整数位
公开(公告)号：US4215415A
公开(公告)日：1980-07-29
申请号：US943836
申请日：1978-09-19
申请人： Akira Kanemasa , Hisashi Sakaguchi
发明人： Akira Kanemasa , Hisashi Sakaguchi
IPC分类号： H03H17/04 , G06F15/34 , G06F7/48
CPC分类号： H03H17/0405 , H03H17/0461
摘要： In a recursive digital filter for dealing with data words given by two's complement representation in a common word format comprising a sign bit, an integer bit, and a predetermined number of fractional bits, an overflow detect and correct circuit is supplied with simultaneously produced sign bits of bit-serial first sum, feedback, and second sum data words and with the integer bit of the second sum data word and detects overflow in the second sum data word to produce, for use in the circuit, an overflow detect pulse indicative of presence or absence of overflow. In either event, the circuit produces an overflow-free data word for use in the filter. When overflow is detected, the circuit produces a polarity decision pulse that decides polarities of the overflow-free bits. Otherwise, the circuit determines the overflow-free bits directly by the corresponding bits of the second sum data word. Use is preferred of a first and a second timing signal which specify time slots for the sign bit and a prescribed bit, respectively, of each serial data words and which are for directly deciding the overflow-free fractional bits by the polarity decision pulse and for producing a second polarity decision pulse for direct decision of polarities of the overflow-free sign and integer bits. A memory having a plurality of memory areas is preferred for production of the overflow detect and the polarity decision pulses and of the overflow-free bits.
摘要翻译：在用于处理包含符号位，整数位和预定数量的分数位的公共字格式的由二进制补码表示给出的数据字的递归数字滤波器中，溢出检测和校正电路被提供同时产生的符号位比特串行第一和，反馈和第二和数据字和第二和数据字的整数位，并且检测第二和数据字中的溢出，以产生用于电路中的指示存在的溢出检测脉冲或不存在溢出。在任一情况下，该电路产生用于滤波器的无溢出数据字。当检测到溢出时，该电路产生极性决定脉冲，其确定无溢出位的极性。否则，电路直接由第二和数据字的相应位确定无溢出位。使用第一和第二定时信号，分别指定每个串行数据字的符号位和规定位的时隙，并且用于通过极性判定脉冲直接确定无溢出分数位，并且对于产生用于直接决定无溢出符号和整数位的极性的第二极性判定脉冲。具有多个存储区域的存储器优选用于产生溢出检测和极性判定脉冲以及无溢出位。

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