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31. 发明授权

US07112499B2 Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal 有权
标题翻译：双级源极/漏极延伸结退火以减少结深度：多脉冲低能激光退火与快速热退火相结合
公开(公告)号：US07112499B2
公开(公告)日：2006-09-26
申请号：US10759671
申请日：2004-01-16
申请人： Chyiu Hyia Poon , Leng Seow Tan , Byung Jin Cho , Alex See , Mousumi Bhat
发明人： Chyiu Hyia Poon , Leng Seow Tan , Byung Jin Cho , Alex See , Mousumi Bhat
IPC分类号： H01L21/336 , H01L21/31 , H01L21/469
CPC分类号： H01L21/268 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L21/823418
摘要： A process is described to form a semiconductor device such as MOSFET or CMOS with shallow junctions in the source/drain extension regions. After forming the shallow trench isolations and the gate stack, sidewall dielectric spacers are removed. A pre-amorphizing implant (PAI) is performed with Ge+ or Si+ ions to form a thin PAI layer on the surface of the silicon regions adjacent to the gate stack. B+ ion implantation is then performed to form source/drain extension (SDE) regions. The B+ implant step is then followed by multiple-pulsed 248 nm KrF excimer laser anneal with pulse duration of 23 ns. This step is to reduce the sheet resistance of the junction through the activation of the boron dopant in the SDE junctions. Laser anneal is then followed by rapid thermal anneal (RTA) to repair the residual damage and also to induce out-diffusion of the boron to yield shallower junctions than the just-implanted junctions prior to RTA.
摘要翻译：描述了一种工艺以在源极/漏极延伸区域中形成具有浅结的诸如MOSFET或CMOS的半导体器件。在形成浅沟槽隔离物和栅极堆叠之后，去除侧壁电介质间隔物。用Ge + +或Si + +离子进行预非晶化植入物（PAI），以在邻近栅叠层的硅区域的表面上形成薄的PAI层。然后进行离子注入以形成源极/漏极延伸（SDE）区域。然后，B + / /> /注入步骤之后是脉冲持续时间为23ns的多脉冲248nm KrF准分子激光退火。该步骤是通过SDE结中的硼掺杂剂的激活来降低结的薄层电阻。然后激光退火之后是快速热退火（RTA）以修复残余损伤，并且还引起硼的扩散，从而产生比RTA之前刚刚植入的结更浅的结。

32. 发明授权

US07091092B2 Process flow for a performance enhanced MOSFET with self-aligned, recessed channel 有权
标题翻译：具有自对准凹陷通道的性能增强型MOSFET的工艺流程
公开(公告)号：US07091092B2
公开(公告)日：2006-08-15
申请号：US10062227
申请日：2002-02-05
申请人： Sneedharan Pillai Sneelal , Francis Poh , James Lee , Alex See , C. K. Lau , Ganesh Shankar Samudra
发明人： Sneedharan Pillai Sneelal , Francis Poh , James Lee , Alex See , C. K. Lau , Ganesh Shankar Samudra
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L29/66545 , H01L29/7834
摘要： A method for forming a self-aligned, recessed channel, MOSFET device that alleviates problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A thin pad oxide layer is grown overlying the substrate and a gate recess, followed by deposition of a thick silicon nitride layer filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown, thickening the pad oxide layer. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown. This forms a tapered oxide layer along the sidewalls of the gate recess. The remaining silicon nitride layer is removed. The oxide layer at the bottom of the gate recess is removed and a gate dielectric layer is grown. Gate polysilicon is deposited filling the gate recess. S/D implantations, metallization, and passivation complete fabrication of the device.
摘要翻译：描述了一种用于形成自对准凹槽的MOSFET器件的方法，该MOSFET器件在减少电极间电容的同时减轻由短沟道和热载流子效应导致的问题。生长覆盖衬底和栅极凹槽的薄衬垫氧化物层，随后沉积填充栅极凹槽的厚氮化硅层。平坦化顶表面暴露氧化垫层。生长另外的氧化物层，使衬垫氧化物层变厚。蚀刻掉氮化硅层的一部分，再次生长另外的氧化物层。这沿着栅极凹槽的侧壁形成锥形氧化物层。剩余的氮化硅层被去除。除去栅极凹部底部的氧化物层，生长栅极电介质层。栅极多晶硅沉积填充栅极凹槽。 S / D注入，金属化和钝化完整的器件制造。

33. 发明授权

US07030451B2 Method and apparatus for performing nickel salicidation 有权
公开(公告)号：US07030451B2
公开(公告)日：2006-04-18
申请号：US11081908
申请日：2005-03-15
申请人： Pooi See Lee , Kin Leong Pey , Alex See , Lap Chan
发明人： Pooi See Lee , Kin Leong Pey , Alex See , Lap Chan
IPC分类号： H01L29/78
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28518 , H01L29/4933
摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

34. 发明授权

US06905964B2 Method of fabricating self-aligned metal barriers by atomic layer deposition on the copper layer 有权
标题翻译：通过原子层沉积在铜层上制造自对准金属屏障的方法
公开(公告)号：US06905964B2
公开(公告)日：2005-06-14
申请号：US10339185
申请日：2003-01-09
申请人： Boon Kiat Lim , Alex See
发明人： Boon Kiat Lim , Alex See
IPC分类号： H01L21/285 , H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76849 , H01L21/28562
摘要： An improved and new process for fabricating self-aligned metal barriers by atomic layer deposition, ALD, capable of producing extremely thin, uniform, and conformal metal barrier films, selectively depositing on copper, not on silicon dioxide interlevel dielectric, in multi-layer dual damascene trench/via processing. Silicon nitride is presently used as a insulating copper barrier. However, silicon nitride has a relatively high dielectric constraint, which deteriorates ICs with increased RC delay. Copper metal barriers of niobium and tantalum have been deposited by atomic layer deposition on copper. With high deposition selectivity, the barrier metal is only deposited over copper, not on silicon dioxide, which eliminates the need of an insulating barrier of silicon nitride.
摘要翻译：一种通过原子层沉积制造自对准金属屏障的改进和新工艺，ALD能够生产极薄，均匀和保形的金属阻挡膜，选择性地沉积在铜上，而不是在二氧化硅层间电介质上沉积在多层双层大马士革沟/通孔加工。氮化硅目前被用作绝缘铜屏障。然而，氮化硅具有相对较高的介电约束，其使具有增加的RC延迟的IC劣化。铌和钽的铜金属屏障已经通过原子层沉积沉积在铜上。具有高的沉积选择性，阻挡金属仅沉积在铜上，而不是在二氧化硅上沉积，这消除了氮化硅的绝缘势垒的需要。

35. 发明授权

US06777329B2 Method to form C54 TiSi2 for IC device fabrication 失效
标题翻译：用于IC器件制造的形成C54 TiSi2的方法
公开(公告)号：US06777329B2
公开(公告)日：2004-08-17
申请号：US09838513
申请日：2001-04-20
申请人： Shaoyin Chen , Ze Xiang Shen , Alex See , Lap Chan
发明人： Shaoyin Chen , Ze Xiang Shen , Alex See , Lap Chan
IPC分类号： H01L2144
CPC分类号： H01L21/28518 , H01L21/268 , H01L21/28052 , H01L29/665
摘要： A novel method for forming a C54 phase titanium disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A titanium layer is deposited overlying the silicon regions to be silicided. The substrate is subjected to a first annealing whereby the titanium is transformed to phase C40 titanium disilicide where it overlies the silicon regions and wherein the titanium not overlying the silicon regions is unreacted. The unreacted titanium layer is removed. The substrate is subjected to a second annealing whereby the phase C40 titanium disilicide is transformed to phase C54 titanium disilicide to complete formation of a phase 54 titanium disilicide film in the manufacture of an integrated circuit.
摘要翻译：描述了在制造集成电路中形成C54相二硅化钛膜的新颖方法。提供具有要被硅化的硅区域的半导体衬底。沉积钛层以硅化硅层。对基板进行第一退火，由此将钛转化为相C40二硅化钛，其中它覆盖在硅区域上，并且其中不覆盖硅区域的钛是未反应的。去除未反应的钛层。对基板进行第二次退火，由此在制造集成电路中相C40二硅化钛转变为C54二硅化钛以完成形成54相的二硅化钛膜。

36. 发明授权

US06650220B2 Parallel spiral stacked inductor on semiconductor material 有权
标题翻译：半导体材料上的平行螺旋堆叠电感
公开(公告)号：US06650220B2
公开(公告)日：2003-11-18
申请号：US10131334
申请日：2002-04-23
申请人： Choon-Beng Sia , Kiat Seng Yeo , Toe Naing Swe , Cheng Yeow Ng , Alex See
发明人： Choon-Beng Sia , Kiat Seng Yeo , Toe Naing Swe , Cheng Yeow Ng , Alex See
IPC分类号： H01F500
CPC分类号： H01L28/10 , H01F17/0013 , H01L23/5227 , H01L27/08 , H01L2924/0002 , Y10T29/4902 , H01L2924/00
摘要： A parallel spiral stacked inductor and manufacturing method therefore is provided. A substrate has a plurality of turns in a plurality of levels, the plurality of turns having a center proximate and a center distal ends. A first plurality of vias connecting the center proximate ends of the plurality of turns and a second plurality of vias connecting the center distal ends of the plurality of turns. A first connecting portion connects to the center proximate ends of the plurality of turns and a second connecting portion connecting to the center distal end of the plurality of turns. A dielectric material contains the inductor.
摘要翻译：因此，提供了一种并联螺旋堆叠电感器及其制造方法。衬底具有多个级的多个匝，多个匝具有中心邻近和中心远端。连接多个匝的中心近端的第一多个通孔和连接多个匝的中心远端的第二多个通孔。第一连接部分连接到多个匝的中心近端，以及连接到多个匝的中心远端的第二连接部分。电介质材料包含电感器。

37. 发明授权

US06602801B2 Method for forming a region of low dielectric constant nanoporous material 有权
标题翻译：形成低介电常数纳米多孔材料区域的方法
公开(公告)号：US06602801B2
公开(公告)日：2003-08-05
申请号：US10012294
申请日：2001-11-13
申请人： Siew Yong Kong , Alex See , Simon Chooi , Gautam Sarkar
发明人： Siew Yong Kong , Alex See , Simon Chooi , Gautam Sarkar
IPC分类号： H01L21469
CPC分类号： H01L21/02126 , H01L21/02118 , H01L21/02203 , H01L21/02282 , H01L21/31695 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , Y10S977/827 , H01L2924/00
摘要： A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of combining a plurality of materials to form a solution. In the present embodiment, the plurality of materials comprising a low dielectric constant material, a pore generator material, and a solvent. In this embodiment, the present method then applies the solution to a surface above which it is desired to form the region of low dielectric constant nanoporous material. Next, the present embodiment subjects the solution, which has been applied to the surface, to a thermal process such that a region of low dielectric constant nanoporous material is formed above the surface.
摘要翻译：公开了一种形成低介电常数纳米多孔材料区域的方法。在一个实施例中，本方法包括组合多种材料以形成溶液的步骤。在本实施例中，包括低介电常数材料，孔发生器材料和溶剂的多种材料。在本实施例中，本方法然后将溶液施加到希望形成低介电常数纳米多孔材料区域的表面上。接下来，本实施例将已经施加到表面的溶液作为热处理，使得在表面上方形成低介电常数纳米多孔材料的区域。

38. 发明授权

US06406975B1 Method for fabricating an air gap shallow trench isolation (STI) structure 失效
标题翻译：制造气隙浅沟槽隔离（STI）结构的方法
公开(公告)号：US06406975B1
公开(公告)日：2002-06-18
申请号：US09721718
申请日：2000-11-27
申请人： Victor Seng Keong Lim , Young-Way Teh , Ting-Cheong Ang , Alex See , Yong Kong Siew
发明人： Victor Seng Keong Lim , Young-Way Teh , Ting-Cheong Ang , Alex See , Yong Kong Siew
IPC分类号： H01L2176
CPC分类号： H01L21/764 , H01L21/76232
摘要： A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.
摘要翻译：制造具有气隙的浅沟槽隔离（STI）的方法，该气隙是通过将有机填充材料分解成盖层形成的。衬底层和阻挡层形成在衬底上。衬垫层和阻挡层被图案化以形成沟槽开口。我们通过蚀刻通过沟槽开口在衬底中形成沟槽。第一衬里层形成在沟槽的侧壁上。在阻挡层和第一衬里层上的第二衬里层。在第二衬垫层上形成填充材料以填充沟槽。在重要的步骤中，覆盖层沉积在填充材料和第二衬里层上。对填充材料进行等离子体处理并加热以使填充材料汽化，使得填充材料通过盖层扩散以形成间隙。绝缘层沉积在覆盖层上。绝缘层被平坦化。去除阻挡层。

39. 发明授权

US06380106B1 Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures 有权
标题翻译：制造气隙金属化方案的方法，其减少互连结构的金属间电容
公开(公告)号：US06380106B1
公开(公告)日：2002-04-30
申请号：US09721719
申请日：2000-11-27
申请人： Seng Keong Victor Lim , Young-way Teh , Ting-Cheong Ang , Alex See , Yong Kong Siew
发明人： Seng Keong Victor Lim , Young-way Teh , Ting-Cheong Ang , Alex See , Yong Kong Siew
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , H01L21/022 , H01L21/02203 , H01L21/02274 , H01L21/31608 , H01L21/7682
摘要： A method of manufacturing a metallization scheme with an air gap formed by vaporizing a filler polymer material. The filler material is covered by a critical permeable dielectric layer. The method begins by forming spaced conductive lines over a semiconductor structure. The spaced conductive lines have top surfaces. A filler material is formed over the spaced conductive lines and the semiconductor structure. The filler material is preferably comprised of a material selected from the group consisting of polypropylene glycol (PPG), polybutadine (PB) polyethylene glycol (PEG), fluorinated amorphous carbon and polycaprolactone diol (PCL) and is formed by a spin on process or a CVD process. We etch back the filler material to expose the top surfaces of the spaced conductive lines. Next, the semiconductor structure is loaded into a HDPCVD chamber. In a critical step, a permeable dielectric layer is formed over the filler material. The permeable dielectric layer has a property of allowing decomposed gas phase filler material to diffuse through. In another critical step, we vaporize the filler material changing the filler material into a vapor phase filler material. The vapor phase filler material diffuses through the permeable dielectric layer to form a gap between the spaced conductive lines. An insulating layer is formed over the permeable dielectric layer.
摘要翻译：一种制造具有通过汽化填料聚合物材料形成气隙的金属化方案的方法。填充材料被临界可渗透的介电层覆盖。该方法开始于在半导体结构上形成间隔的导线。间隔的导线具有顶表面。在间隔的导线和半导体结构之上形成填充材料。填充材料优选由选自聚丙二醇（PPG），聚丁二烯（PB）聚乙二醇（PEG），氟化无定形碳和聚己内酯二醇（PCL）组成的组中的材料组成，并且通过旋涂工艺或 CVD工艺。我们回蚀填充材料以暴露间隔的导线的顶表面。接下来，将半导体结构加载到HDPCVD室中。在关键步骤中，在填充材料上形成可渗透介电层。可渗透介电层具有允许分解的气相填充材料扩散通过的性质。在另一个关键步骤中，我们将填充材料蒸发成将填料材料变成气相填料。气相填充材料通过可渗透的介电层扩散以在间隔的导线之间形成间隙。在可渗透介电层上形成绝缘层。

40. 发明授权

US06281082B1 Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill 有权
标题翻译：用于形成具有公共浅沟槽隔离和层间介质间隙填充的MOS晶体管的方法
公开(公告)号：US06281082B1
公开(公告)日：2001-08-28
申请号：US09524526
申请日：2000-03-13
申请人： Feng Chen , Kok Hin Teo , Kok Hiang Tang , Alex See
发明人： Feng Chen , Kok Hin Teo , Kok Hiang Tang , Alex See
IPC分类号： H01L2176
CPC分类号： H01L29/66545 , H01L21/76237
摘要： A new method of forming MOS transistors in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. A pad oxide layer is deposited. A silicon nitride layer is deposited. Trenches are patterned for planned shallow trench isolations. The sidewalls of the trenches are oxidized. A photoresist layer is deposited overlying the silicon nitride layer and filling the trenches. The photoresist layer is etched down to below the top surface of the silicon nitride layer. The silicon nitride layer is patterned to form dummy gate electrodes. Sidewall spacers are formed on the dummy gate electrodes. The photoresist layer is removed. A dielectric layer is deposited overlying the dummy gate electrodes and the trenches. The dielectric layer is polished down to the top surface of the dummy gate electrodes to thereby complete the STI and the ILD. The dummy gate electrodes are etched away. A gate oxide layer is formed. A gate electrode layer is deposited overlying the dielectric layer and filling the openings for the planned transistor gates. The gate electrode layer is polished down to form the transistor gates, and the integrated circuit is completed.
摘要翻译：已经实现了在制造集成电路器件中形成MOS晶体管的新方法。提供半导体衬底。沉积衬垫氧化物层。沉积氮化硅层。沟槽图案化为规划的浅沟槽隔离。沟槽的侧壁被氧化。沉积覆盖氮化硅层并填充沟槽的光致抗蚀剂层。光致抗蚀剂层被蚀刻到氮化硅层的顶表面下方。图案化氮化硅层以形成伪栅电极。在虚拟栅电极上形成侧壁间隔物。去除光致抗蚀剂层。沉积覆盖在虚拟栅电极和沟槽上的电介质层。电介质层被抛光到虚拟栅电极的顶表面，从而完成STI和ILD。伪栅电极被蚀刻掉。形成栅氧化层。沉积覆盖在电介质层上的栅极电极层，并填充用于计划的晶体管栅极的开口。将栅极电极层进行抛光以形成晶体管栅极，并且集成电路完成。

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