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1. 发明授权

US06281082B1 Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill 有权
标题翻译：用于形成具有公共浅沟槽隔离和层间介质间隙填充的MOS晶体管的方法
公开(公告)号：US06281082B1
公开(公告)日：2001-08-28
申请号：US09524526
申请日：2000-03-13
申请人： Feng Chen , Kok Hin Teo , Kok Hiang Tang , Alex See
发明人： Feng Chen , Kok Hin Teo , Kok Hiang Tang , Alex See
IPC分类号： H01L2176
CPC分类号： H01L29/66545 , H01L21/76237
摘要： A new method of forming MOS transistors in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. A pad oxide layer is deposited. A silicon nitride layer is deposited. Trenches are patterned for planned shallow trench isolations. The sidewalls of the trenches are oxidized. A photoresist layer is deposited overlying the silicon nitride layer and filling the trenches. The photoresist layer is etched down to below the top surface of the silicon nitride layer. The silicon nitride layer is patterned to form dummy gate electrodes. Sidewall spacers are formed on the dummy gate electrodes. The photoresist layer is removed. A dielectric layer is deposited overlying the dummy gate electrodes and the trenches. The dielectric layer is polished down to the top surface of the dummy gate electrodes to thereby complete the STI and the ILD. The dummy gate electrodes are etched away. A gate oxide layer is formed. A gate electrode layer is deposited overlying the dielectric layer and filling the openings for the planned transistor gates. The gate electrode layer is polished down to form the transistor gates, and the integrated circuit is completed.
摘要翻译：已经实现了在制造集成电路器件中形成MOS晶体管的新方法。提供半导体衬底。沉积衬垫氧化物层。沉积氮化硅层。沟槽图案化为规划的浅沟槽隔离。沟槽的侧壁被氧化。沉积覆盖氮化硅层并填充沟槽的光致抗蚀剂层。光致抗蚀剂层被蚀刻到氮化硅层的顶表面下方。图案化氮化硅层以形成伪栅电极。在虚拟栅电极上形成侧壁间隔物。去除光致抗蚀剂层。沉积覆盖在虚拟栅电极和沟槽上的电介质层。电介质层被抛光到虚拟栅电极的顶表面，从而完成STI和ILD。伪栅电极被蚀刻掉。形成栅氧化层。沉积覆盖在电介质层上的栅极电极层，并填充用于计划的晶体管栅极的开口。将栅极电极层进行抛光以形成晶体管栅极，并且集成电路完成。

2. 发明授权

US06380066B1 Methods for eliminating metal corrosion by FSG 有权
标题翻译：消除金属腐蚀的方法
公开(公告)号：US06380066B1
公开(公告)日：2002-04-30
申请号：US09531783
申请日：2000-03-21
申请人： Alex See , Kok Hin Teo , Kok Hiang Tang
发明人： Alex See , Kok Hin Teo , Kok Hiang Tang
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/02071 , H01L21/31053 , H01L21/31629 , H01L21/32136 , H01L21/76802 , H01L21/76834
摘要： A method of fabricating metal plugs within via openings comprising the following steps. A semiconductor substrate having an overlying metal layer and oxide hard masks overlying the metal layer is provided. The oxide hard masks are used to etch the metal layer to form metal lines separated by metal line openings. An oxide liner is formed over the etched structure. A layer of FSG is deposited over the oxide liner. The FSG layer is then planarized to remove: the excess of the FSG layer from the etched structure; and the portions of the oxide liner over the oxide hard masks to form FSG blocks within the metal line openings. A cap layer is formed over the planarized structure. The cap layer and hard masks are then planarized to form via openings exposing the metal lines. Planarized metal plugs are then within the via openings.
摘要翻译：一种在通孔内制造金属塞的方法，包括以下步骤。提供了具有覆盖金属层和覆盖金属层的氧化物硬掩模的半导体衬底。氧化物硬掩模用于蚀刻金属层以形成由金属线开口分开的金属线。在蚀刻结构上形成氧化物衬垫。一层FSG沉积在氧化物衬垫上。然后将FSG层平坦化以除去：来自蚀刻结构的过量的FSG层; 并且氧化物衬垫的部分在氧化物硬掩模上，以在金属线开口内形成FSG块。在平坦化结构上形成覆盖层。然后将盖层和硬掩模平坦化以形成暴露金属线的通孔。平面化的金属插头然后在通孔开口内。

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