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    • 39. 发明申请
    • POWER-ON RESET CIRCUIT AND METHOD
    • 上电复位电路和方法
    • US20130106473A1
    • 2013-05-02
    • US13281921
    • 2011-10-26
    • Bruce M. NewmanDean A. BadilloReimund RebelKlaus Juergen SchoepfMohammad Asmani
    • Bruce M. NewmanDean A. BadilloReimund RebelKlaus Juergen SchoepfMohammad Asmani
    • H03L7/00
    • H03L5/00H03K17/223
    • The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.
    • 所公开的上电复位电路提供电源电压Vdd何时以及是否达到触发电压电平Vtrig的指示。 所公开的电路包括触发器电路和第一比较器电路。 根据本发明的电路具有耦合到电源电压的触发器电路的D输入节点。 第一比较器电路输出时钟信号,其中触发电路由时钟信号计时。 触发电路的Q输出节点提供上电复位信号,当供电电压处于小于触发电压电平Vtrig的电压电平时,上电复位信号处于LO状态。 当电源电压处于大于触发电压电平Vtrig的电压电平时,上电复位信号处于HI状态。
    • 40. 发明授权
    • Power-on reset circuit and method
    • 上电复位电路及方法
    • US08415993B1
    • 2013-04-09
    • US13281921
    • 2011-10-26
    • Bruce M. NewmanDean A. BadilloReimund RebelKlaus Juergen SchoepfMohammad Asmani
    • Bruce M. NewmanDean A. BadilloReimund RebelKlaus Juergen SchoepfMohammad Asmani
    • H03L7/00
    • H03L5/00H03K17/223
    • The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.
    • 所公开的上电复位电路提供电源电压Vdd何时以及是否达到触发电压电平Vtrig的指示。 所公开的电路包括触发器电路和第一比较器电路。 根据本发明的电路具有耦合到电源电压的触发器电路的D输入节点。 第一比较器电路输出时钟信号,其中触发电路由时钟信号计时。 触发电路的Q输出节点提供上电复位信号,当供电电压处于小于触发电压电平Vtrig的电压电平时,上电复位信号处于LO状态。 当电源电压处于大于触发电压电平Vtrig的电压电平时,上电复位信号处于HI状态。