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1. 发明申请

US20130106473A1 POWER-ON RESET CIRCUIT AND METHOD 有权
标题翻译：上电复位电路和方法
公开(公告)号：US20130106473A1
公开(公告)日：2013-05-02
申请号：US13281921
申请日：2011-10-26
申请人： Bruce M. Newman , Dean A. Badillo , Reimund Rebel , Klaus Juergen Schoepf , Mohammad Asmani
发明人： Bruce M. Newman , Dean A. Badillo , Reimund Rebel , Klaus Juergen Schoepf , Mohammad Asmani
IPC分类号： H03L7/00
CPC分类号： H03L5/00 , H03K17/223
摘要： The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.
摘要翻译：所公开的上电复位电路提供电源电压Vdd何时以及是否达到触发电压电平Vtrig的指示。所公开的电路包括触发器电路和第一比较器电路。根据本发明的电路具有耦合到电源电压的触发器电路的D输入节点。第一比较器电路输出时钟信号，其中触发电路由时钟信号计时。触发电路的Q输出节点提供上电复位信号，当供电电压处于小于触发电压电平Vtrig的电压电平时，上电复位信号处于LO状态。当电源电压处于大于触发电压电平Vtrig的电压电平时，上电复位信号处于HI状态。

2. 发明授权

US08415993B1 Power-on reset circuit and method 有权
标题翻译：上电复位电路及方法
公开(公告)号：US08415993B1
公开(公告)日：2013-04-09
申请号：US13281921
申请日：2011-10-26
申请人： Bruce M. Newman , Dean A. Badillo , Reimund Rebel , Klaus Juergen Schoepf , Mohammad Asmani
发明人： Bruce M. Newman , Dean A. Badillo , Reimund Rebel , Klaus Juergen Schoepf , Mohammad Asmani
IPC分类号： H03L7/00
CPC分类号： H03L5/00 , H03K17/223
摘要： The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.
摘要翻译：所公开的上电复位电路提供电源电压Vdd何时以及是否达到触发电压电平Vtrig的指示。所公开的电路包括触发器电路和第一比较器电路。根据本发明的电路具有耦合到电源电压的触发器电路的D输入节点。第一比较器电路输出时钟信号，其中触发电路由时钟信号计时。触发电路的Q输出节点提供上电复位信号，当供电电压处于小于触发电压电平Vtrig的电压电平时，上电复位信号处于LO状态。当电源电压处于大于触发电压电平Vtrig的电压电平时，上电复位信号处于HI状态。

3. 发明授权

US07535391B1 Analog-to-digital converter having random capacitor assignment and method thereof 失效
标题翻译：具有随机电容器分配的模数转换器及其方法
公开(公告)号：US07535391B1
公开(公告)日：2009-05-19
申请号：US11969982
申请日：2008-01-07
申请人： Bruce M. Newman , Douglas A. Garrity
发明人： Bruce M. Newman , Douglas A. Garrity
IPC分类号： H03M1/20
CPC分类号： H03M1/0673 , H03M1/16 , H03M1/38 , H03M1/804
摘要： An analog-to-digital converter (ADC) includes a multiplying digital-to-analog converter (MDAC) having a plurality of capacitors and a plurality of capacitor positions. The ADC generates a random number for a conversion cycle. The ADC configures each capacitor of the plurality of capacitors in a corresponding capacitor position of the plurality of capacitor positions based on the random number for the conversion cycle. The ADC converts, for the conversion cycle, a voltage of an analog signal to a digital value based on the capacitor configurations.
摘要翻译：模数转换器（ADC）包括具有多个电容器和多个电容器位置的倍增数模转换器（MDAC）。 ADC为转换周期生成一个随机数。 ADC基于转换周期的随机数，将多个电容器中的每个电容器配置在多个电容器位置的相应电容器位置。在转换周期，ADC会根据电容器配置将模拟信号的电压转换为数字值。

4. 发明授权

US07898353B2 Clock conditioning circuit 有权
标题翻译：时钟调理电路
公开(公告)号：US07898353B2
公开(公告)日：2011-03-01
申请号：US12466987
申请日：2009-05-15
申请人： Merit Y. Hong , Bruce M. Newman
发明人： Merit Y. Hong , Bruce M. Newman
IPC分类号： H03K3/00 , H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： H03K5/15 , G06F1/10
摘要： A circuit includes a clock conditioning circuit which receives an encoded clock signal, and provides first and second conditioned clock signals in response. The clock conditioning circuit adjusts a period of the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal. The circuit includes a modulator which receives the first and second conditioned clock signals.
摘要翻译：电路包括时钟调节电路，其接收经编码的时钟信号，并响应地提供第一和第二调节时钟信号。时钟调节电路响应于编码时钟信号的周期的调整来调整第一和第二调节时钟信号的周期。该电路包括接收第一和第二调节时钟信号的调制器。

5. 发明申请

US20100289538A1 CLOCK CONDITIONING CIRCUIT 有权
标题翻译：时钟调节电路
公开(公告)号：US20100289538A1
公开(公告)日：2010-11-18
申请号：US12466987
申请日：2009-05-15
申请人： Merit Y. Hong , Bruce M. Newman
发明人： Merit Y. Hong , Bruce M. Newman
IPC分类号： H03L7/00 , H03K3/017 , H03H11/16
CPC分类号： H03K5/15 , G06F1/10
摘要： A circuit includes a clock conditioning circuit which receives an encoded clock signal, and provides first and second conditioned clock signals in response. The clock conditioning circuit adjusts a period of the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal. The circuit includes a modulator which receives the first and second conditioned clock signals.
摘要翻译：电路包括时钟调节电路，其接收经编码的时钟信号，并且响应地提供第一和第二调节时钟信号。时钟调节电路响应于编码时钟信号的周期的调整来调整第一和第二调节时钟信号的周期。该电路包括接收第一和第二调节时钟信号的调制器。

6. 发明授权

US08022850B2 Multiple-bit, digital-to-analog converters and conversion methods 有权
标题翻译：多位数模转换器和转换方法
公开(公告)号：US08022850B2
公开(公告)日：2011-09-20
申请号：US12566953
申请日：2009-09-25
申请人： Bruce M. Newman
发明人： Bruce M. Newman
IPC分类号： H03M1/66
CPC分类号： H03M1/0665 , H03M1/74 , H03M3/464 , H03M3/502
摘要： Embodiments include DACs and methods for digital-to-analog conversion. A DAC includes an encoder and a plurality of DAC elements. The encoder maps each of a plurality of bits of a digital input value to one of the DAC elements, and produces a sign indication indicating whether a magnitude of the digital input value is above or below a threshold. Each DAC element produces a DAC element analog output signal that indicates whether a received sign indication and a received bit corresponds to a first state, a second state or a third state (e.g., a zero, positive or negative state). In an embodiment, the DAC uses positive historic mapping information when the magnitude of the digital input value is above the threshold, and negative historic mapping information when the magnitude of the digital input value is below the threshold. DAC elements may be configurable into a Return-to-Zero or a Non-Return-to-Zero mode.
摘要翻译：实施例包括用于数模转换的DAC和方法。 DAC包括编码器和多个DAC元件。编码器将数字输入值的多个位中的每一个映射到DAC元件中的一个，并且产生表示数字输入值的大小是高于还是低于阈值的符号指示。每个DAC元件产生DAC元件模拟输出信号，该DAC元件模拟输出信号指示接收到的符号指示和接收的比特是否对应于第一状态，第二状态或第三状态（例如，零，正或负状态）。在一个实施例中，当数字输入值的大小高于阈值时，DAC使用正历史映射信息，当数字输入值的幅度低于阈值时，DAC使用负历史映射信息。 DAC元件可以被配置为归零或非归零模式。

7. 发明申请

US20110074613A1 MULTIPLE-BIT, DIGITAL-TO-ANALOG CONVERTERS AND CONVERSION METHODS 有权
标题翻译：多位数转换器和转换方法
公开(公告)号：US20110074613A1
公开(公告)日：2011-03-31
申请号：US12566953
申请日：2009-09-25
申请人： Bruce M. Newman
发明人： Bruce M. Newman
IPC分类号： H03M1/66 , H03M3/00
CPC分类号： H03M1/0665 , H03M1/74 , H03M3/464 , H03M3/502
摘要： Embodiments include DACs and methods for digital-to-analog conversion. A DAC includes an encoder and a plurality of DAC elements. The encoder maps each of a plurality of bits of a digital input value to one of the DAC elements, and produces a sign indication indicating whether a magnitude of the digital input value is above or below a threshold. Each DAC element produces a DAC element analog output signal that indicates whether a received sign indication and a received bit corresponds to a first state, a second state or a third state (e.g., a zero, positive or negative state). In an embodiment, the DAC uses positive historic mapping information when the magnitude of the digital input value is above the threshold, and negative historic mapping information when the magnitude of the digital input value is below the threshold. DAC elements may be configurable into a Return-to-Zero or a Non-Return-to-Zero mode.
摘要翻译：实施例包括用于数模转换的DAC和方法。 DAC包括编码器和多个DAC元件。编码器将数字输入值的多个位中的每一个映射到DAC元件中的一个，并且产生表示数字输入值的大小是高于还是低于阈值的符号指示。每个DAC元件产生DAC元件模拟输出信号，该DAC元件模拟输出信号指示接收到的符号指示和接收的比特是否对应于第一状态，第二状态或第三状态（例如，零，正或负状态）。在一个实施例中，当数字输入值的大小高于阈值时，DAC使用正历史映射信息，当数字输入值的幅度低于阈值时，DAC使用负历史映射信息。 DAC元件可以被配置为归零或非归零模式。

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