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1. 发明申请

US20180097521A1 Method and Apparatus for Calibration of Voltage Controlled Oscillator 审中-公开
公开(公告)号：US20180097521A1
公开(公告)日：2018-04-05
申请号：US15676080
申请日：2017-08-14
申请人： Apple Inc.
发明人： Joachim S. Hammerschmidt , Robert G. Lorenz
IPC分类号： H03L7/089 , H03C3/09 , H03L7/099 , H03L7/10 , H03L7/18
CPC分类号： H03L7/0893 , H03B5/1243 , H03B5/1265 , H03B2201/025 , H03B2201/0266 , H03C3/0925 , H03C3/0933 , H03C3/095 , H03C3/0958 , H03C3/0991 , H03J2200/10 , H03L7/0805 , H03L7/0996 , H03L7/104 , H03L7/105 , H03L7/18 , H03L7/189 , H03L2207/06
摘要： A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

2. 发明申请

US20180062661A1 SPREAD SPECTRUM CLOCK GENERATOR 有权
公开(公告)号：US20180062661A1
公开(公告)日：2018-03-01
申请号：US15251065
申请日：2016-08-30
申请人： STMicroelectronics International N.V.
发明人： Anand Kumar , Gagan Midha
IPC分类号： H03L7/093 , H03L7/099 , H03L7/089 , H03L7/197
CPC分类号： H03L7/093 , H03C3/095 , H03L7/0891 , H03L7/099 , H03L7/1976 , H04B1/69
摘要： A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.

3. 发明申请

US20170371990A1 MODEL-BASED CALIBRATION OF AN ALL-DIGITAL PHASE LOCKED LOOP 审中-公开
公开(公告)号：US20170371990A1
公开(公告)日：2017-12-28
申请号：US15192278
申请日：2016-06-24
申请人： QUALCOMM Incorporated
发明人： Magnus Olov WIKLUND , Emanuele LOPELLI , Charles WANG
IPC分类号： G06F17/50 , H04W88/02 , H03L7/093 , H03L7/099
CPC分类号： G06F17/5036 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03C3/0991 , H03L7/093 , H03L7/0991 , H03L2207/12 , H03L2207/50 , H04W88/02
摘要： A method of calibrating an All-Digital Phase Locked Loop (ADPLL) includes obtaining a model of the ADPLL and applying an input signal to both the ADPLL and to the model. The ADPLL generates an actual output of the ADPLL, while the model generates a model output. An error between the actual output of the ADPLL and the model output is then sensed. The method also includes generating a calibration value based on the error between the actual output of the ADPLL and the model output, and adjusting a feedforward gain of the ADPLL based on the calibration value.

4. 发明授权

US08669796B2 Clock generator, semiconductor device, and clock generating method 有权
标题翻译：时钟发生器，半导体器件和时钟发生方法
公开(公告)号：US08669796B2
公开(公告)日：2014-03-11
申请号：US13738781
申请日：2013-01-10
申请人： Renesas Electronics Corporation
发明人： Yoshinori Kanda
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , H03C3/095 , H03C3/0966
摘要： There is provided a clock generator for generating a modulation waveform which is high in the effect of suppressing a spectrum and making a circuit scale smaller than a modulation system using the Hershey-kiss waveform. More specifically, a modulation waveform generation unit generates a tangent waveform or a tangent+triangular waveform as an SSCG modulation waveform and provides an oscillator with a signal in which the SSCG modulation waveform is combined with the output of a low pass filter of a PLL loop.
摘要翻译：提供了一种时钟发生器，用于产生抑制频谱效果高的调制波形，并使电路规模比使用本氏吻合波形的调制系统小。更具体地，调制波形生成单元生成切线波形或切线+三角波形作为SSCG调制波形，并且向振荡器提供其中SSCG调制波形与PLL环路的低通滤波器的输出组合的信号。

5. 发明授权

US08634512B2 Two point modulation digital phase locked loop 有权
标题翻译：双点调制数字锁相环
公开(公告)号：US08634512B2
公开(公告)日：2014-01-21
申请号：US13023369
申请日：2011-02-08
申请人： Lai Kan Leung , Chiewcharn Narathong
发明人： Lai Kan Leung , Chiewcharn Narathong
IPC分类号： H03D3/24
CPC分类号： H04L27/20 , H03C3/0941 , H03C3/095 , H03C3/0975
摘要： A two point modulation digital phase locked loop circuit is disclosed. The circuit includes a sampling clock input that is switchable between a plurality of frequencies. The circuit also includes a sigma-delta modulator in a feedback path that receives low-pass modulation data. The circuit also includes a voltage-mode digital-to-analog converter (VDAC) that receives high-pass modulation data. The circuit also includes an analog voltage controlled oscillator coupled to the feedback path and the output of the VDAC. The circuit also includes a phase-to-digital converter (PDC) coupled to the feedback path, the sampling clock and a loop filter.
摘要翻译：公开了一种双点调制数字锁相环电路。电路包括可在多个频率之间切换的采样时钟输入。电路还包括接收低通调制数据的反馈路径中的Σ-Δ调制器。该电路还包括接收高通调制数据的电压模式数模转换器（VDAC）。该电路还包括耦合到反馈路径和VDAC的输出的模拟压控振荡器。电路还包括耦合到反馈路径的相对数字转换器（PDC），采样时钟和环路滤波器。

6. 发明授权

US08509373B2 Apparatus and method for generating small-size spread spectrum clock signal 有权
标题翻译：用于产生小尺寸扩频时钟信号的装置和方法
公开(公告)号：US08509373B2
公开(公告)日：2013-08-13
申请号：US12635553
申请日：2009-12-10
申请人： Ha-Jun Jeon , Sang-Seob Kim
发明人： Ha-Jun Jeon , Sang-Seob Kim
IPC分类号： H03D3/24
CPC分类号： H04B1/69 , H03B23/00 , H03C3/0925 , H03C3/0941 , H03C3/095
摘要： An apparatus and method for generating a small-size spread spectrum clock signal that can include generating a reference clock signal by dividing an external clock signal, detecting frequency and phase differences between a reference clock signal and a comparison clock signal as error signals, modulating a controlled voltage corresponding to the current in accordance with a modulation control signal, outputting an oscillation clock signal having a frequency oscillated according to the modulated controlled voltage as a spectrum-spread version of the external clock signal, and generating the comparison clock signal by dividing the oscillation clock signal, and then compensating for the modulation of the controlled voltage in accordance with a demodulation magnitude that is generated for use in compensating for the modulation magnitude.
摘要翻译：一种用于产生小尺寸扩频时钟信号的装置和方法，其可以包括通过划分外部时钟信号产生参考时钟信号，检测基准时钟信号和比较时钟信号之间的频率和相位差作为误差信号，调制根据调制控制信号对应于电流的受控电压，输出具有根据调制控制电压振荡的频率的振荡时钟信号作为外部时钟信号的频谱扩展版本，并通过将振荡时钟信号，然后根据产生用于补偿调制幅度的解调幅度补偿受控电压的调制。

7. 发明申请

US20130093524A1 DIGITALLY CONTROLLED OSCILLATOR DEVICE AND HIGH FREQUENCY SIGNAL PROCESSING DEVICE 有权
标题翻译：数字控制振荡器装置和高频信号处理装置
公开(公告)号：US20130093524A1
公开(公告)日：2013-04-18
申请号：US13651410
申请日：2012-10-13
申请人： Renesas Mobile Corporation
发明人： Takahiro NAKAMURA
IPC分类号： H03L7/02
CPC分类号： H03L7/02 , H03B5/1206 , H03B5/1265 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03L7/099 , H03L2207/50
摘要： The present invention provides a digitally controlled oscillator device capable of reducing noise away from an oscillation frequency, and a high frequency signal processing device. Fractional capacitances are realized using a plurality of unitary capacitor units, for example. In one unitary capacitor unit, one ends of two types of capacitive elements are respectively coupled to oscillation output nodes. On the other hand, in the unitary capacitor units other than the one unitary capacitor unit, one ends of two types of capacitive elements are respectively coupled to a fixed voltage. The other ends of one capacitive elements in all the unitary capacitor units are coupled in common, and the other ends of other capacitive elements are also coupled in common. Turning on and off of respective switches in all the unitary capacitor units are controlled in common.
摘要翻译：本发明提供一种能够降低远离振荡频率的噪声的数字控制振荡器装置和高频信号处理装置。例如，使用多个单体电容器单元实现分数电容。在一个单体电容器单元中，两种类型的电容元件的一端分别耦合到振荡输出节点。另一方面，除了一个单一电容器单元之外的单电容器单元中，两种类型的电容元件的一端分别耦合到固定电压。所有单体电容器单元中的一个电容元件的另一端共同耦合，并且其它电容元件的另一端也共同耦合。所有单体电容器单元中的各个开关的导通和关断被共同控制。

8. 发明授权

US08364098B2 PLL calibration 有权
标题翻译： PLL校准
公开(公告)号：US08364098B2
公开(公告)日：2013-01-29
申请号：US12771900
申请日：2010-04-30
申请人： Timothy John Ridgers
发明人： Timothy John Ridgers
IPC分类号： H04B1/04 , H03C3/06 , H03C3/09
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0991
摘要： A method for applying a modulation signal to a phase locked loop comprises filtering the modulation signal to provide a low frequency component and a high frequency for application to respectively the feedback and feedforward paths of a phase locked loop. The high frequency component is scaled by a gain factor before being applied to the feedforward path. The low frequency component is also scaled by a gain factor and applied to the feedforward path. The energy in a common low frequency range of the modulation signal and of the loop error signal is estimated, and the gain factors are modified dependent on the measured energy.
摘要翻译：将调制信号施加到锁相环的方法包括对调制信号进行滤波以提供低频分量和高频，以分别应用于锁相环的反馈和前馈路径。在施加到前馈路径之前，高频分量被增益因子缩放。低频分量也被增益因子缩放并应用于前馈路径。估计调制信号和环路误差信号的共同低频范围内的能量，并根据测得的能量修改增益因子。

9. 发明申请

US20110151856A1 OSCILLATORS HAVING ARBITRARY FREQUENCIES AND RELATED SYSTEMS AND METHODS 有权
公开(公告)号：US20110151856A1
公开(公告)日：2011-06-23
申请号：US12721472
申请日：2010-03-10
申请人： Reimund Rebel , Klaus Juergen Schoepf , Jan H. Kuypers
发明人： Reimund Rebel , Klaus Juergen Schoepf , Jan H. Kuypers
IPC分类号： H04W4/00 , H04L27/00
CPC分类号： H03B5/30 , H03B5/32 , H03B19/00 , H03C3/095 , H03J7/065 , H03L7/0991 , H03L7/18 , H03L7/197 , H04B1/40
摘要： Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

10. 发明授权

US07884676B1 PLL/FLL circuit with gain control 有权
标题翻译：带增益控制的PLL / FLL电路
公开(公告)号：US07884676B1
公开(公告)日：2011-02-08
申请号：US12534663
申请日：2009-08-03
申请人： Kenji Miyanaga
发明人： Kenji Miyanaga
IPC分类号： H03L7/00
CPC分类号： H03L7/093 , H03C3/0941 , H03C3/095 , H03C3/0966
摘要： An FLL circuit having a capability of configuring a desired loop bandwidth in a short period of time is provided. An FDC 17 generates a feedback of an output signal of a VCO 15. An error detector 11 detects an error of the output signal of the VCO 15. A voltage retainer 13 retains an output of a control voltage of the VCO 15. A reference signal generator 16 generates a reference signal. An adder 14 adds the reference signal to a control voltage outputted by the voltage retainer 13. A Kv calculator 18 calculates a gain Kv of the VCO 15 based on a degree of transition of an output frequency of the VCO 15. A loop bandwidth controller 19 adjusts, based on the gain Kv of the VCO 15, a gain of a loop filter 12 to an optimum value, and configures a desired loop bandwidth.
摘要翻译：提供了具有在短时间内配置期望的环路带宽的能力的FLL电路。 FDC17产生VCO15的输出信号的反馈。误差检测器11检测VCO15的输出信号的误差。电压保持器13保持VCO15的控制电压的输出。参考信号发生器16产生参考信号。加法器14将参考信号与由电压保持器13输出的控制电压相加.Kv计算器18基于VCO15的输出频率的转变程度来计算VCO 15的增益Kv。环路带宽控制器19 基于VCO15的增益Kv将环路滤波器12的增益调整到最佳值，并且配置期望的环路带宽。

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