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    • 1. 发明申请
    • POWER-ON RESET CIRCUIT AND METHOD
    • 上电复位电路和方法
    • US20130106473A1
    • 2013-05-02
    • US13281921
    • 2011-10-26
    • Bruce M. NewmanDean A. BadilloReimund RebelKlaus Juergen SchoepfMohammad Asmani
    • Bruce M. NewmanDean A. BadilloReimund RebelKlaus Juergen SchoepfMohammad Asmani
    • H03L7/00
    • H03L5/00H03K17/223
    • The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.
    • 所公开的上电复位电路提供电源电压Vdd何时以及是否达到触发电压电平Vtrig的指示。 所公开的电路包括触发器电路和第一比较器电路。 根据本发明的电路具有耦合到电源电压的触发器电路的D输入节点。 第一比较器电路输出时钟信号,其中触发电路由时钟信号计时。 触发电路的Q输出节点提供上电复位信号,当供电电压处于小于触发电压电平Vtrig的电压电平时,上电复位信号处于LO状态。 当电源电压处于大于触发电压电平Vtrig的电压电平时,上电复位信号处于HI状态。
    • 2. 发明授权
    • Power-on reset circuit and method
    • 上电复位电路及方法
    • US08415993B1
    • 2013-04-09
    • US13281921
    • 2011-10-26
    • Bruce M. NewmanDean A. BadilloReimund RebelKlaus Juergen SchoepfMohammad Asmani
    • Bruce M. NewmanDean A. BadilloReimund RebelKlaus Juergen SchoepfMohammad Asmani
    • H03L7/00
    • H03L5/00H03K17/223
    • The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.
    • 所公开的上电复位电路提供电源电压Vdd何时以及是否达到触发电压电平Vtrig的指示。 所公开的电路包括触发器电路和第一比较器电路。 根据本发明的电路具有耦合到电源电压的触发器电路的D输入节点。 第一比较器电路输出时钟信号,其中触发电路由时钟信号计时。 触发电路的Q输出节点提供上电复位信号,当供电电压处于小于触发电压电平Vtrig的电压电平时,上电复位信号处于LO状态。 当电源电压处于大于触发电压电平Vtrig的电压电平时,上电复位信号处于HI状态。
    • 3. 发明授权
    • Variable phase amplifier circuit and method of use
    • 可变相位放大器电路及其使用方法
    • US08395456B2
    • 2013-03-12
    • US13049738
    • 2011-03-16
    • Dean A. BadilloReimund RebelKlaus Juergen Schoepf
    • Dean A. BadilloReimund RebelKlaus Juergen Schoepf
    • H03B5/30
    • H03G3/004H03B5/30H03F3/45071H03H11/22
    • A variable phase amplifier circuit is disclosed and its method of use in tuning devices having resonators. The variable phase amplifier receives an input differential signal pair. The input differential signal pair can be generated by a resonator device. The variable phase amplifier generates a modified differential signal pair in response to receiving the input differential signal pair. The variable phase amplifier provides a means to vary the phase of the modified differential signal pair with respect to the input differential signal pair, in an accurate and stable manner. If the modified differential signal pair with a phase shift introduced in it is fed back to the resonator device, the resonator will change its frequency of oscillation, where the new frequency of oscillation is a function of the phase of the modified differential signal pair.
    • 公开了一种可变相位放大器电路及其在具有谐振器的调谐装置中的使用方法。 可变相位放大器接收输入差分信号对。 输入差分信号对可以由谐振器装置产生。 响应于接收到输入差分信号对,可变相位放大器产生修正的差分信号对。 可变相位放大器提供了以准确和稳定的方式改变修改的差分信号对相对于输入差分信号对的相位的装置。 如果将其中引入的相移的修正的差分信号对反馈到谐振器装置,则谐振器将改变其振荡频率,其中新的振荡频率是修改的差分信号对的相位的函数。
    • 4. 发明申请
    • VARIABLE PHASE AMPLIFIER CIRCUIT AND METHOD OF USE
    • 可变相放大器电路及其使用方法
    • US20110163819A1
    • 2011-07-07
    • US13049738
    • 2011-03-16
    • Dean A. BadilloReimund RebelKlaus Juergen Schoepf
    • Dean A. BadilloReimund RebelKlaus Juergen Schoepf
    • H03B5/24H03H11/20
    • H03G3/004H03B5/30H03F3/45071H03H11/22
    • A variable phase amplifier circuit is disclosed and its method of use in tuning devices having resonators. The variable phase amplifier receives an input differential signal pair. The input differential signal pair can be generated by a resonator device. The variable phase amplifier generates a modified differential signal pair in response to receiving the input differential signal pair. The variable phase amplifier provides a means to vary the phase of the modified differential signal pair with respect to the input differential signal pair, in an accurate and stable manner. If the modified differential signal pair with a phase shift introduced in it is fed back to the resonator device, the resonator will change its frequency of oscillation, where the new frequency of oscillation is a function of the phase of the modified differential signal pair.
    • 公开了一种可变相位放大器电路及其在具有谐振器的调谐装置中的使用方法。 可变相位放大器接收输入差分信号对。 输入差分信号对可以由谐振器装置产生。 响应于接收到输入差分信号对,可变相位放大器产生修正的差分信号对。 可变相位放大器提供了以准确和稳定的方式改变修改的差分信号对相对于输入差分信号对的相位的装置。 如果将其中引入的相移的修正的差分信号对反馈到谐振器装置,则谐振器将改变其振荡频率,其中新的振荡频率是修改的差分信号对的相位的函数。
    • 5. 发明授权
    • Method and apparatus for managing arbitrary frequencies
    • 用于管理任意频率的方法和装置
    • US08791762B2
    • 2014-07-29
    • US13272587
    • 2011-10-13
    • Reimund RebelKlaus Juergen Schoepf
    • Reimund RebelKlaus Juergen Schoepf
    • H03L7/00
    • H03L7/22H03K23/66H03L7/185
    • Frequency synthesizers for use with oscillators that generate an arbitrary frequency are described, as well as related devices and methods. Divider information can be generated or otherwise accessed for use in configuring a phase lock loop device that is adapted for coupling with the oscillator, where the phase lock loop device can include a plurality of integer dividers without utilizing a fractional divider, where the divider information can include frequency deviations corresponding to groups of integer divider settings for the phase lock loop device, and where each deviation of the frequency deviations can be based on a frequency differential between a standard operating frequency and an output frequency for the phase lock loop utilizing one group of integer divider settings from the groups of integer divider settings.
    • 描述了与产生任意频率的振荡器一起使用的频率合成器,以及相关的装置和方法。 可以生成或以其他方式访问分频器信息以用于配置适于与振荡器耦合的锁相环装置,其中锁相环装置可以包括多个整数除数器而不使用分数分频器,其中分频器信息可以 包括对应于锁相环装置的整数分频器设置组的频率偏差,并且其中频偏的每个偏差可以基于使用一组的锁相环的锁相环的标准工作频率和输出频率之间的频率差 来自整数分频器设置组的整数分频器设置。