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31. 发明授权

US06429500B1 Semiconductor pin diode for high frequency applications 失效
标题翻译：半导体二极管用于高频应用
公开(公告)号：US06429500B1
公开(公告)日：2002-08-06
申请号：US09670587
申请日：2000-09-29
申请人： David R. Greenberg , Kathryn T. Schonenberg , Seshadri Subbanna , Keith M. Walter
发明人： David R. Greenberg , Kathryn T. Schonenberg , Seshadri Subbanna , Keith M. Walter
IPC分类号： H01L31075
CPC分类号： H01L29/66098 , H01L29/868
摘要： A microwave PIN diode having an increased intrinsic region volume for storing a charge. A semiconductor substrate has an N+ subcollector/cathode layer which encloses a region of the substrate. An N-skin formed over the interior of enclosed region. An Si layer is formed over the subcollector/cathode and N-skin to a thickness which defines the thickness for the intrinsic region of the diode. Implants are formed in the Si layer to permit contact with the subcollector/cathode layer. An anode is formed on the top of the Si layer. The total volume of the intrinsic region is increased by the N-skin which is positioned below the surface of the subcollector/cathode. The PIN diode may be formed as a lateral PIN diode thereby increasing the intrinsic region volume even further.
摘要翻译：具有增加的用于存储电荷的本征区域体积的微波PIN二极管。半导体衬底具有封装衬底的区域的N +子集电极/阴极层。在封闭区域的内部形成的N皮。在子集电极/阴极和N皮层上形成Si层，其厚度限定了二极管本征区域的厚度。在Si层中形成植入物以允许与子集电极/阴极层接触。阳极形成在Si层的顶部。本征区域的总体积由位于子集电极/阴极表面下方的N面增加。 PIN二极管可以形成为侧向PIN二极管，从而进一步增加本征区域体积。

32. 发明授权

US08455322B2 Silicon germanium heterojunction bipolar transistor structure and method 有权
标题翻译：硅锗异质结双极晶体管结构及方法
公开(公告)号：US08455322B2
公开(公告)日：2013-06-04
申请号：US12719212
申请日：2010-03-08
申请人： Oleg Gluschenkov , Rajendran Krishnasamy , Kathryn T. Schonenberg
发明人： Oleg Gluschenkov , Rajendran Krishnasamy , Kathryn T. Schonenberg
IPC分类号： H01L21/8242
CPC分类号： H01L29/66242 , H01L21/2253 , H01L21/26513 , H01L21/324 , H01L29/0821 , H01L29/0826 , H01L29/1004 , H01L29/7378
摘要： Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.
摘要翻译：公开了一种改进的半导体结构（例如，硅锗（SiGe）异质结双极晶体管），其具有窄的基本上无间隙的SIC基座，其外部基极具有最小的重叠。此外，公开了一种形成晶体管的方法，该晶体管使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本无间隙的集电极。因此，所得到的SiGe HBT晶体管可以用比传统技术可以实现的更窄的基极和集电极空间电荷区域来制造。

33. 发明申请

US20090243031A1 STRUCTURE AND METHOD TO CONTROL OXIDATION IN HIGH-K GATE STRUCTURES 有权
标题翻译：控制高K门结构氧化的结构和方法
公开(公告)号：US20090243031A1
公开(公告)日：2009-10-01
申请号：US12055682
申请日：2008-03-26
申请人： Wesley C. Natzle , Renee T. Mo , Rashmi Jha , Kathryn T. Schonenberg , Richard A. Conti
发明人： Wesley C. Natzle , Renee T. Mo , Rashmi Jha , Kathryn T. Schonenberg , Richard A. Conti
IPC分类号： H01L29/49 , H01L21/441
CPC分类号： H01L21/76224 , H01L21/28123 , H01L29/517
摘要： In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.
摘要翻译：在一个实施例中，本发明提供一种制造半导体器件的方法，其包括提供包括至少一个半导体区域和至少一个氧源区域的衬底; 在所述至少一个氧区的上表面的部分顶部形成氧阻隔材料; 在包括所述至少一个半导体区域的衬底上形成高k栅极电介质，其中氧阻挡材料将所述高k栅极电介质与所述至少一个氧源材料分离; 并在高k栅极电介质的顶部形成栅极导体。

34. 发明申请

US20070284674A1 POROUS SILICON FOR ISOLATION REGION FORMATION AND RELATED STRUCTURE 失效
标题翻译：用于隔离区形成的多孔硅和相关结构
公开(公告)号：US20070284674A1
公开(公告)日：2007-12-13
申请号：US11423286
申请日：2006-06-09
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Kathryn T. Schonenberg , Thomas A. Wallner
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Kathryn T. Schonenberg , Thomas A. Wallner
IPC分类号： H01L29/94
CPC分类号： H01L29/16 , H01L29/66242 , H01L29/7371
摘要： A method of forming an isolation region using porous silicon and a related structure are disclosed. One embodiment of the method may include forming a collector region; forming a porous silicon region in the collector region; forming a crystalline silicon intrinsic base layer over the collector region, the intrinsic base layer extending over a portion of the porous silicon region to form an extrinsic base; and forming an isolation region in the porous silicon region. The method is applicable to forming an HBT having a structure including a crystalline silicon intrinsic base extending beyond a collector region and extending over an isolation region to form a continuous intrinsic-to-extrinsic base conduction path of low resistance. The HBT has improved performance by having a smaller collector to intrinsic base interface and larger intrinsic base to extrinsic base interface.
摘要翻译：公开了使用多孔硅形成隔离区域的方法和相关结构。该方法的一个实施例可以包括形成收集区域; 在集电区域形成多孔硅区域; 在所述集电极区上形成晶体硅本征基极层，所述本征基极层在所述多孔硅区域的一部分上延伸以形成外部基极; 以及在所述多孔硅区域中形成隔离区域。该方法适用于形成具有包括结晶硅本征基底的结构的HBT，该晶体硅本征基极延伸超过集电极区域并在隔离区域上延伸以形成具有低电阻的连续本征至外在的基极传导路径。 HBT通过使内部基本接口具有较小的集电极和较大的内在基极到外部基极接口来提高性能。

35. 发明授权

US06869852B1 Self-aligned raised extrinsic base bipolar transistor structure and method 失效
标题翻译：自对准凸极本征双极晶体管结构及方法
公开(公告)号：US06869852B1
公开(公告)日：2005-03-22
申请号：US10707756
申请日：2004-01-09
申请人： Alvin J. Joseph , Qizhi Liu , BethAnn Rainey , Kathryn T. Schonenberg
发明人： Alvin J. Joseph , Qizhi Liu , BethAnn Rainey , Kathryn T. Schonenberg
IPC分类号： H01L21/331 , H01L29/10 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242
摘要： A method of fabricating a bipolar transistor structure that provides unit current gain frequency (fT) and maximum oscillation frequency (fMAX) improvements of a raised extrinsic base using non-self-aligned techniques to establish a self-aligned structure. Accordingly, the invention eliminates the complexity and cost of current self-aligned raised extrinsic base processes. The invention forms a raised extrinsic base and an emitter opening over a landing pad, i.e., etch stop layer, then replaces the landing pad with a conductor that is converted, in part, to an insulator. An emitter is then formed in the emitter opening once the insulator is removed from the emitter opening. An unconverted portion of the conductor provides a conductive base link and a remaining portion of the insulator under a spacer isolates the extrinsic base from the emitter while maintaining self-alignment of the emitter to the extrinsic base. The invention also includes the resulting bipolar transistor structure.
摘要翻译：一种制造双极晶体管结构的方法，其使用非自对准技术建立自对准结构来提供升高的外部基极的单位电流增益频率（fT）和最大振荡频率（fMAX）改善。因此，本发明消除了当前自对准引起的外在基本过程的复杂性和成本。本发明形成凸起的非本征基极和在着陆焊盘（即，蚀刻停止层）上开口的发射体，然后用部分转换为绝缘体的导体代替着陆焊盘。一旦绝缘体从发射极开口移除，就在发射极开口中形成发射极。导体的未转换部分提供导电基极连接，并且在间隔物下方的绝缘体的剩余部分将外部基极与发射极隔离，同时保持发射极到外部基极的自对准。本发明还包括所得到的双极晶体管结构。

36. 发明授权

US06844225B2 Self-aligned mask formed utilizing differential oxidation rates of materials 失效
标题翻译：使用材料的不同氧化速率形成的自对准掩模
公开(公告)号：US06844225B2
公开(公告)日：2005-01-18
申请号：US10345469
申请日：2003-01-15
申请人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
发明人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
IPC分类号： H01L21/321 , H01L21/331 , H01L29/732 , H01L29/737 , H01L21/00
CPC分类号： H01L29/66242 , H01L21/32105 , Y10S438/911
摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.
摘要翻译：使用不同材料的不同氧化速率形成自对准氧化物掩模。自对准氧化物掩模形成在CVD生长的基底NPN基层上，其牺牲了场上的活性区域上的单晶Si（或Si / SiGe）和多晶Si（或Si / SiGe）。通过利用多晶硅（或Si / SiGe）比单晶Si（或Si / SiGe）更快地氧化的事实来制造自对准掩模。通过使用热氧化工艺在多晶硅（或Si / siGe）和单晶Si（或Si / siGe）上形成氧化膜，以在多晶硅（或Si / SiGe）上形成厚的氧化层，以及在单晶Si（或Si / siGe）上方的薄氧化层，随后进行受控氧化物蚀刻以除去单晶Si（或Si / siGe）上的薄氧化层，同时将自对准氧化物掩模层留在多晶硅（或Si / siGe）。然后在自对准掩模形成之后形成隆起的外在基体。该自对准氧化物掩模阻挡从扩展的外在碱基到收集器角的扩散。

37. 发明授权

US06744079B2 Optimized blocking impurity placement for SiGe HBTs 有权
标题翻译：优化SiGe HBT的阻塞杂质位置
公开(公告)号：US06744079B2
公开(公告)日：2004-06-01
申请号：US09683983
申请日：2002-03-08
申请人： Basanth Jagannathan , Alvin J. Joseph , Xuefeng Liu , Kathryn T. Schonenberg , Ryan W. Wuthrich
发明人： Basanth Jagannathan , Alvin J. Joseph , Xuefeng Liu , Kathryn T. Schonenberg , Ryan W. Wuthrich
IPC分类号： H01L31072
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/161 , H01L29/7378
摘要： A high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20% and a boron-doped base region formed therein having a thickness. The base region includes diffusion-limiting impurities substantially throughout its thickness, at a peak concentration below that of boron in the base region. Both the base region and the diffusion-limiting impurities are positioned relative to a peak concentration of Ge in the SiGe layer so as to optimize both performance and yield.
摘要翻译：具有峰值Ge浓度至少为20％的SiGe层和其中形成有硼掺杂基底区域的高性能SiGe HBT具有厚度。碱性区域在其整个厚度上基本上包括扩散限制性杂质，峰值浓度低于碱性区域中硼的峰值浓度。碱性区域和扩散限制杂质都相对于SiGe层中的Ge的峰值浓度定位，以便优化性能和产率。

38. 发明授权

US06534371B2 C implants for improved SiGe bipolar yield 有权
公开(公告)号：US06534371B2
公开(公告)日：2003-03-18
申请号：US09878605
申请日：2001-06-11
申请人： Douglas D. Coolbaugh , Kathryn T. Schonenberg
发明人： Douglas D. Coolbaugh , Kathryn T. Schonenberg
IPC分类号： H01L21331
CPC分类号： H01L29/7378 , H01L21/26506 , H01L29/1004 , H01L29/1012 , H01L29/66242 , H01L29/66318
摘要： A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

39. 发明授权

US06448124B1 Method for epitaxial bipolar BiCMOS 失效
标题翻译：外延双极BiCMOS的方法
公开(公告)号：US06448124B1
公开(公告)日：2002-09-10
申请号：US09439067
申请日：1999-11-12
申请人： Douglas D. Coolbaugh , James S. Dunn , Peter J. Geiss , Peter B. Gray , David L. Harame , Kathryn T. Schonenberg , Stephen A. St. Onge , Seshadri Subbanna
发明人： Douglas D. Coolbaugh , James S. Dunn , Peter J. Geiss , Peter B. Gray , David L. Harame , Kathryn T. Schonenberg , Stephen A. St. Onge , Seshadri Subbanna
IPC分类号： H01L218238
CPC分类号： H01L21/76224 , H01L21/763 , H01L21/8249
摘要： A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.
摘要翻译：提供一种形成BiCMOS集成电路的方法，其包括以下步骤：（a）在衬底的第一区域中形成双极器件的第一部分; （b）在所述第一区域上形成第一保护层以保护所述双极器件的所述第一部分; （c）在所述衬底的第二区域中形成场效应晶体管器件; （d）在所述衬底的所述第二区域上形成第二保护层以保护所述场效应晶体管器件; （e）去除所述第一保护层; （f）在所述衬底的所述第一区域中形成所述双极器件的第二部分; 和（g）去除所述第二保护层。

40. 发明授权

US07919379B2 Dielectric spacer removal 有权
标题翻译：介质垫片去除
公开(公告)号：US07919379B2
公开(公告)日：2011-04-05
申请号：US11852906
申请日：2007-09-10
申请人： Eduard A. Cartier , Rashmi Jha , Sivananda Kanakasabapathy , Xi Li , Renee T. Mo , Vijay Narayanan , Vamsi Paruchuri , Mark T. Robson , Kathryn T. Schonenberg , Michelle L. Steen , Richard Wise , Ying Zhang
发明人： Eduard A. Cartier , Rashmi Jha , Sivananda Kanakasabapathy , Xi Li , Renee T. Mo , Vijay Narayanan , Vamsi Paruchuri , Mark T. Robson , Kathryn T. Schonenberg , Michelle L. Steen , Richard Wise , Ying Zhang
IPC分类号： H01L21/00 , H01L21/336
CPC分类号： H01L21/31116 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.
摘要翻译：本发明涉及半导体器件，更具体地说，涉及一种基本上不去除半导体衬底去除对半导体衬底的表面有选择性的介电隔离层的工艺和结构。本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。该方法包括在半导体衬底上形成场效应晶体管，所述FET包括电介质间隔物和所述栅极结构，所述电介质隔离物邻近所述栅极结构的侧壁并位于所述半导体衬底中的源极/漏极区域上; 在FET上沉积第一氮化物层; 并且基本上不去除半导体衬底，去除对半导体衬底的选择性的氮化物层和电介质衬垫。

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