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1. 发明授权

US06303975B1 Low noise, high frequency solid state diode 有权
标题翻译：低噪声，高频固态二极管
公开(公告)号：US06303975B1
公开(公告)日：2001-10-16
申请号：US09436166
申请日：1999-11-09
申请人： Robert A. Groves , Dominique Nguyen-Ngoc , Dale K. Jadus , Keith M. Walter
发明人： Robert A. Groves , Dominique Nguyen-Ngoc , Dale K. Jadus , Keith M. Walter
IPC分类号： H01L2710
CPC分类号： H01L27/1021 , H01L29/861 , Y10S257/91
摘要： A low noise, high frequency solid state diode is provided from a plurality of unit diode cells which are interconnected in parallel. Each of the unit diode cells forms an element of an array having rows and columns of unit diode cells. The diode cells include a base region of polysilicon, forming an anode, and an active cathode region which forms a diode junction with the anode. A plurality of overlapping subcollector regions interconnect the cathode regions, to provide a single, continuous collector for the diode arrays. The base region has a minimum perimeter to area ratio which reduces the resistance of each active diode region. A plurality of cathode contacts are connected to the subcollector through a respective reach region of highly doped semiconductor material. One or more metalization layers connect the cathode regions together, and the anodes of the base regions together. By controlling the size and shape of the base region of polysilicon, the series resistance of the resulting diode is minimized.
摘要翻译：从并联的多个单位二极管单元提供低噪声，高频固态二极管。每个单位二极管单元形成具有单位二极管单元的行和列的阵列的元件。二极管单元包括形成阳极的多晶硅的基极区域和与阳极形成二极管结的活性阴极区域。多个重叠子集电极区域互连阴极区域，为二极管阵列提供单一的连续集电极。基极区域具有最小的周边面积比，其减小了每个有源二极管区域的电阻。多个阴极触点通过高掺杂半导体材料的相应到达区域连接到子集电极。一个或多个金属化层将阴极区域连接在一起，并将基极区域的阳极连接在一起。通过控制多晶硅的基极区域的尺寸和形状，所得二极管的串联电阻最小化。

2. 发明授权

US06429500B1 Semiconductor pin diode for high frequency applications 失效
标题翻译：半导体二极管用于高频应用
公开(公告)号：US06429500B1
公开(公告)日：2002-08-06
申请号：US09670587
申请日：2000-09-29
申请人： David R. Greenberg , Kathryn T. Schonenberg , Seshadri Subbanna , Keith M. Walter
发明人： David R. Greenberg , Kathryn T. Schonenberg , Seshadri Subbanna , Keith M. Walter
IPC分类号： H01L31075
CPC分类号： H01L29/66098 , H01L29/868
摘要： A microwave PIN diode having an increased intrinsic region volume for storing a charge. A semiconductor substrate has an N+ subcollector/cathode layer which encloses a region of the substrate. An N-skin formed over the interior of enclosed region. An Si layer is formed over the subcollector/cathode and N-skin to a thickness which defines the thickness for the intrinsic region of the diode. Implants are formed in the Si layer to permit contact with the subcollector/cathode layer. An anode is formed on the top of the Si layer. The total volume of the intrinsic region is increased by the N-skin which is positioned below the surface of the subcollector/cathode. The PIN diode may be formed as a lateral PIN diode thereby increasing the intrinsic region volume even further.
摘要翻译：具有增加的用于存储电荷的本征区域体积的微波PIN二极管。半导体衬底具有封装衬底的区域的N +子集电极/阴极层。在封闭区域的内部形成的N皮。在子集电极/阴极和N皮层上形成Si层，其厚度限定了二极管本征区域的厚度。在Si层中形成植入物以允许与子集电极/阴极层接触。阳极形成在Si层的顶部。本征区域的总体积由位于子集电极/阴极表面下方的N面增加。 PIN二极管可以形成为侧向PIN二极管，从而进一步增加本征区域体积。

3. 发明授权

US06423603B1 Method of forming a microwave array transistor for low-noise and high-power applications 有权
公开(公告)号：US06423603B1
公开(公告)日：2002-07-23
申请号：US09921656
申请日：2001-08-06
申请人： Robert A. Groves , Dale K. Jadus , Dominique L. Nguyen-Ngoc , Keith M. Walter
发明人： Robert A. Groves , Dale K. Jadus , Dominique L. Nguyen-Ngoc , Keith M. Walter
IPC分类号： H01L21331
摘要： A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

4. 发明授权

US06426547B1 Lateral polysilicon pin diode and method for so fabricating 失效
标题翻译：侧面多晶硅pin二极管及其制造方法
公开(公告)号：US06426547B1
公开(公告)日：2002-07-30
申请号：US09734624
申请日：2000-12-12
申请人： David R. Greenberg , Dale K. Jadus , Seshadri Subbanna , Keith M. Walter
发明人： David R. Greenberg , Dale K. Jadus , Seshadri Subbanna , Keith M. Walter
IPC分类号： H01L31075
CPC分类号： H01L29/868
摘要： The invention provides a PIN diode having a laterally extended I-region. The invention also provides a method of fabricating the inventive PIN diode compatible with modern RF technologies such as silicon-germanium BiCMOS processes.
摘要翻译：本发明提供了具有横向延伸的I区的PIN二极管。本发明还提供了一种制造本发明的PIN二极管的方法，该PIN二极管与诸如硅 - 锗BiCMOS工艺的现代RF技术兼容。

5. 发明授权

US5399512A Method of making carrier conduction conductor-insulator semiconductor (CIS) transistor 失效
标题翻译：制造载流子导体绝缘体半导体（CIS）晶体管的方法
公开(公告)号：US5399512A
公开(公告)日：1995-03-21
申请号：US280742
申请日：1994-07-26
申请人： Shaikh N. Mohammad , Robert B. Renbeck , Keith M. Walter
发明人： Shaikh N. Mohammad , Robert B. Renbeck , Keith M. Walter
IPC分类号： H01L21/331 , H01L29/165 , H01L29/73 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66242 , H01L29/7311 , H01L29/7371
摘要： A Conductor Insulator Semiconductor (CIS) heterojunction transistor. The CIS transistor is on silicon (Si) substrate. A layer of n type Si is deposited on the substrate. A trench is formed through the n type Si layer, and may extend slightly into the substrate. The trench is filled with an insulator, preferably SiO.sub.2. A layer of p type Si.sub.1-z Ge.sub.z (where z is the mole fraction of Ge and 0.1.ltoreq.z.ltoreq.0.9) is deposited on the n type Si layer. A p.sup.+ base contact region is defined in the p type Si.sub.1-z Ge.sub.z region above the oxide filled trench. A n type dopant is ion implanted into both the Si.sub.1-z Ge.sub.z and n Si layers and may extend slightly into the substrate, forming a collector region. A thin oxide layer is deposited on the Si.sub.1-z Ge.sub.z layer and a low work function metal such as Al, Mg, Mn, or Ti is selectively deposited on the thin oxide and to define an emitter. Alternatively, the emitter may be p.sup.+ polysilicon. Next, the thin oxide is opened to define collector and base contacts. A suitable metal, such as Al is deposited in the base and collector contacts.
摘要翻译：导体绝缘体半导体（CIS）异质结晶体管。 CIS晶体管在硅（Si）衬底上。在衬底上沉积一层n型Si。通过n型Si层形成沟槽，并且可以稍微延伸到衬底中。沟槽填充有绝缘体，优选SiO 2。 p型Si1-z Gez（其中z是Ge的摩尔分数和0.1≤n≤0.9）沉积在n型Si层上。在氧化物填充沟槽上方的p型Si1-z Gez区域中限定了p +基极接触区域。将n型掺杂剂离子注入到Si1-z Gez和nSi层中，并且可以稍微延伸到衬底中，形成集电极区域。在Si1-zGez层上沉积薄的氧化物层，并且在薄氧化物上选择性地沉积诸如Al，Mg，Mn或Ti的低功函数金属并限定发射极。或者，发射极可以是p +多晶硅。接下来，打开薄氧化物以限定集电极和基极触点。合适的金属如Al沉积在基极和集电极触点中。

6. 发明授权

US5382815A Carrier conduction conductor-insulator semiconductor (CIS) transistor 失效
标题翻译：载体导体绝缘体半导体（CIS）晶体管
公开(公告)号：US5382815A
公开(公告)日：1995-01-17
申请号：US173388
申请日：1993-12-23
申请人： Shaikh N. Mohammad , Robert B. Renbeck , Keith M. Walter
发明人： Shaikh N. Mohammad , Robert B. Renbeck , Keith M. Walter
IPC分类号： H01L21/331 , H01L29/165 , H01L29/73 , H01L29/737 , H01L31/072 , H01L27/082 , H01L29/00 , H01L31/109
CPC分类号： H01L29/66242 , H01L29/7311 , H01L29/7371
摘要： A Conductor Insulator Semiconductor (CIS) heterojunction transistor. The CIS transistor is on silicon (Si) substrate. A layer of n type Si is deposited on the substrate. A trench is formed through the n type Si layer, and may extend slightly into the substrate. The trench is filled with an insulator, preferably SiO.sub.2. A layer of p type Si.sub.1-z Ge.sub.z (where z is the mole fraction of Ge and 0.1.ltoreq.z.ltoreq.0.9) is deposited on the n type Si layer. A p.sup.+ base contact region is defined in the p type Si.sub.1-z Ge.sub.z region above the oxide filled trench. A n type dopant is ion implanted into both the Si.sub.1-z Ge.sub.z and n Si layers and may extend slightly into the substrate, forming a collector region. A thin oxide layer is deposited on the Si.sub.1-z Ge.sub.z layer and a low work function metal such as Al, Mg, Mn, or Ti is selectively deposited on the thin oxide and to define an emitter. Alternatively, the emitter may be p.sup.+ polysilicon. Next, the thin oxide is opened to define collector and base contacts. A suitable metal, such as Al is deposited in the base and collector contacts.
摘要翻译：导体绝缘体半导体（CIS）异质结晶体管。 CIS晶体管在硅（Si）衬底上。在衬底上沉积一层n型Si。通过n型Si层形成沟槽，并且可以稍微延伸到衬底中。沟槽填充有绝缘体，优选SiO 2。 p型Si1-z Gez（其中z是Ge的摩尔分数和0.1≤n≤0.9）沉积在n型Si层上。在氧化物填充沟槽上方的p型Si1-z Gez区域中限定了p +基极接触区域。将n型掺杂剂离子注入到Si1-z Gez和nSi层中，并且可以稍微延伸到衬底中，形成集电极区域。在Si1-zGez层上沉积薄的氧化物层，并且在薄氧化物上选择性地沉积诸如Al，Mg，Mn或Ti的低功函数金属并限定发射极。或者，发射极可以是p +多晶硅。接下来，打开薄氧化物以限定集电极和基极触点。合适的金属如Al沉积在基极和集电极触点中。

7. 发明授权

US06762479B2 Microwave array transistor for low-noise and high-power applications 失效
标题翻译：微波阵列晶体管用于低噪声和高功率应用
公开(公告)号：US06762479B2
公开(公告)日：2004-07-13
申请号：US09187243
申请日：1998-11-06
申请人： Robert A. Groves , Dale K. Jadus , Dominique L. Nguyen-Ngoc , Keith M. Walter
发明人： Robert A. Groves , Dale K. Jadus , Dominique L. Nguyen-Ngoc , Keith M. Walter
IPC分类号： H01L27082
CPC分类号： H01L29/73 , H01L27/0823 , H01L29/0692
摘要： A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.
摘要翻译：一种包括多个晶体管的晶体管阵列。每个晶体管包括发射极。发射极区域接触覆盖每个发射极区域。至少一个基极区域位于每个发射极区域的下面，并且对阵列中的多个晶体管是共同的。至少一个基极接触覆盖至少一个基极区域并与每个晶体管相关联。多个基极触点对于阵列中的至少两个晶体管是共同的。至少一个集电极通过与每个晶体管相关联。通过接触覆盖的收集器覆盖每个收集器到达。导电材料的埋层子集电极区域将集电极到达区域电连接到每个晶体管的集电极基座区域。

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