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31. 发明授权

US6107869A Semiconductor integrated circuit 失效
公开(公告)号：US6107869A
公开(公告)日：2000-08-22
申请号：US96456
申请日：1998-06-11
申请人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
发明人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
IPC分类号： G11C11/41 , G11C5/14 , G11C8/08 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/3205 , H01L21/822 , H01L21/8242 , H01L23/52 , H01L27/04 , H01L27/108 , G05F3/02
CPC分类号： G11C8/08 , G11C5/14 , G11C5/147 , H01L2924/0002
摘要： It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.

32. 发明授权

US5966341A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5966341A
公开(公告)日：1999-10-12
申请号：US982398
申请日：1997-12-02
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C11/4097 , H01L21/8242 , H01L27/105 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10805 , G11C11/408 , G11C11/4096 , G11C11/4097 , G11C7/10 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

33. 发明授权

US5953242A System with meshed power and signal buses on cell array 失效
公开(公告)号：US5953242A
公开(公告)日：1999-09-14
申请号：US991727
申请日：1997-12-16
申请人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
发明人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
IPC分类号： G11C11/401 , G11C5/02 , G11C5/14 , G11C7/06 , G11C7/18 , G11C8/14 , G11C11/34 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/025 , G11C5/14 , G11C7/065 , G11C7/18 , G11C8/14
摘要： A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

34. 发明授权

US5881005A Semiconductor integrated circuit device having a constant delay-time circuit for different operating voltages 失效
标题翻译：具有用于不同工作电压的恒定延迟时间电路的半导体集成电路器件
公开(公告)号：US5881005A
公开(公告)日：1999-03-09
申请号：US782400
申请日：1997-01-13
申请人： Hiroshi Otori , Takesada Akiba
发明人： Hiroshi Otori , Takesada Akiba
IPC分类号： G11C11/409 , G11C7/06 , G11C11/401 , G11C11/407 , G11C11/408 , G11C7/00
CPC分类号： G11C7/06
摘要： The present invention is a method and apparatus for overdriving signals received by a sense amplifier circuit. To this end, an overdrive circuit comprising an n-channel common source switch drives the signal to be sensed for a period of time to a voltage level greater than a normal level. The period of time the signal is overdriven corresponds to the operating voltage of the sense amplifier circuit. Upon completion of the overdriving, a normalization circuit drives the signal to be sensed for a second period of time to the normal level, thereby preparing it for the next memory cycle so that the signals can be once again set to the desired precharge level.
摘要翻译：本发明是一种用于过驱动由读出放大器电路接收的信号的方法和装置。为此，包括n沟道公共源开关的过驱动电路将要被感测的信号一段时间驱动到大于正常电平的电压电平。信号过驱动的时间段对应于读出放大器电路的工作电压。在完成过驱动时，归一化电路将要被感测的信号第二时间段驱动到正常电平，从而将其准备用于下一个存储周期，使得信号可以被再次设置为期望的预充电电平。

35. 发明授权

US5448526A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5448526A
公开(公告)日：1995-09-05
申请号：US282311
申请日：1994-07-29
申请人： Masashi Horiguchi , Kiyoo Itoh , Yoshiki Kawajiri , Goro Kitsukawa , Takayuki Kawahara , Takesada Akiba
发明人： Masashi Horiguchi , Kiyoo Itoh , Yoshiki Kawajiri , Goro Kitsukawa , Takayuki Kawahara , Takesada Akiba
IPC分类号： G01R31/317 , G05F3/24 , G11C5/14 , G11C13/00
CPC分类号： G11C5/147 , G01R31/31715 , G05F3/24
摘要： An intermediate voltage generating circuit for generating a voltage lying between an external power supply voltage and a ground voltage, and two voltage limiter circuits for generating internal power supply voltages and stabilized with this intermediate voltage as a reference are provided in a semiconductor integrated circuit. Even if the external power supply voltage or the ground voltage fluctuates, no disagreement is produced between a logical threshold of a circuit operating on the external power supply voltage and a logical threshold of a circuit operating on the internal power supply voltage.
摘要翻译：在半导体集成电路中设置有用于产生位于外部电源电压和接地电压之间的电压的中间电压产生电路和用于产生内部电源电压并以该中间电压稳定的两个限压器电路。即使外部电源电压或接地电压发生波动，也不会在外部电源电压工作的电路的逻辑阈值与内部电源电压的电路的逻辑阈值之间产生不同意见。

36. 发明授权

US5347492A Semiconductor integrated circuit device 失效
公开(公告)号：US5347492A
公开(公告)日：1994-09-13
申请号：US152387
申请日：1993-11-16
申请人： Masashi Horiguchi , Kiyoo Itoh , Yoshiki Kawajiri , Goro Kitsukawa , Takayuki Kawahara , Takesada Akiba
发明人： Masashi Horiguchi , Kiyoo Itoh , Yoshiki Kawajiri , Goro Kitsukawa , Takayuki Kawahara , Takesada Akiba
IPC分类号： G01R31/317 , G05F3/24 , G11C5/14 , G11C13/00
CPC分类号： G11C5/147 , G01R31/31715 , G05F3/24
摘要： An intermediate voltage generating circuit for generating a voltage lying between an external power supply voltage and a ground voltage, and two voltage limiter circuits for generating internal power supply voltages and stabilized with this intermediate voltage as a reference are provided in a semiconductor integrated circuit. Even if the external power supply voltage or the ground voltage fluctuates, no disagreement is produced between a logical threshold of a circuit operating on the external power supply voltage and a logical threshold of a circuit operating on the internal power supply voltage.

37. 发明授权

US08325524B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08325524B2
公开(公告)日：2012-12-04
申请号：US12903774
申请日：2010-10-13
申请人： Yasushi Oka , Tadashi Omae , Takesada Akiba
发明人： Yasushi Oka , Tadashi Omae , Takesada Akiba
IPC分类号： G11C14/00
CPC分类号： G11C5/025 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.
摘要翻译：包括非易失性存储器的半导体器件的芯片面积减小。半导体器件包括形成在基板的主表面上并彼此相邻布置的第一存储单元和第二存储单元。在基板的主表面上布置有彼此电隔离的有源区。在第一有源区域中，布置第一存储单元的电容器元件，而第二存储单元的电容器元件布置在第四有源区域中。在第二有源区域中，布置有第一和第二存储单元的相应写/擦除元件。此外，在第三有源区域中，布置有第一和第二存储单元的各个读取元件。

38. 发明申请

US20110024814A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20110024814A1
公开(公告)日：2011-02-03
申请号：US12903774
申请日：2010-10-13
申请人： Yasushi OKA , Tadashi Omae , Takesada Akiba
发明人： Yasushi OKA , Tadashi Omae , Takesada Akiba
IPC分类号： H01L27/108
CPC分类号： G11C5/025 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.
摘要翻译：包括非易失性存储器的半导体器件的芯片面积减小。半导体器件包括形成在基板的主表面上并彼此相邻布置的第一存储单元和第二存储单元。在基板的主表面上布置有彼此电隔离的有源区。在第一有源区域中，布置第一存储单元的电容器元件，而第二存储单元的电容器元件布置在第四有源区域中。在第二有源区域中，布置有第一和第二存储单元的相应写/擦除元件。此外，在第三有源区域中，布置有第一和第二存储单元的各个读取元件。

39. 发明申请

US20110012906A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR DRIVING LIQUID CRYSTAL DISPLAY 有权
标题翻译：用于驱动液晶显示器的半导体集成电路装置
公开(公告)号：US20110012906A1
公开(公告)日：2011-01-20
申请号：US12890642
申请日：2010-09-25
申请人： Yasushi KAWASE , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
发明人： Yasushi KAWASE , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
IPC分类号： G06F12/02
CPC分类号： G09G3/3655 , G09G5/005 , G09G2310/08 , H01L27/0207 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.
摘要翻译：本发明实现了一种用于驱动液晶（液晶控制驱动器IC）的半导体集成电路器件，其能够根据要使用的液晶显示器的规格容易地设定驱动条件等。在用于驱动液晶显示器的半导体集成电路器件中提供电可编程非易失性存储器电路（EPROM）或电可擦除和可编程的非易失性存储器电路（EEPROM），并将设置信息存储在存储器电路中。存储电路由与其他电路的形成器件的半导体制造工艺相同的工艺形成的普通器件构成。

40. 发明授权

US07839683B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07839683B2
公开(公告)日：2010-11-23
申请号：US12233580
申请日：2008-09-18
申请人： Yasushi Oka , Tadashi Omae , Takesada Akiba
发明人： Yasushi Oka , Tadashi Omae , Takesada Akiba
IPC分类号： G11C14/00
CPC分类号： G11C5/025 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.
摘要翻译：包括非易失性存储器的半导体器件的芯片面积减小。半导体器件包括形成在基板的主表面上并彼此相邻布置的第一存储单元和第二存储单元。在基板的主表面上布置有彼此电隔离的有源区。在第一有源区域中，布置第一存储单元的电容器元件，而第二存储单元的电容器元件布置在第四有源区域中。在第二有源区域中，布置有第一和第二存储单元的相应写/擦除元件。此外，在第三有源区域中，布置有第一和第二存储单元的各个读取元件。

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