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1. 发明授权

US06512257B2 System with meshed power and signal buses on cell array 有权
公开(公告)号：US06512257B2
公开(公告)日：2003-01-28
申请号：US10120872
申请日：2002-04-11
申请人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
发明人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
IPC分类号： H01L31119
CPC分类号： G11C8/14 , G11C5/025 , G11C5/14 , G11C7/065 , G11C7/18
摘要： A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

2. 发明授权

US06259280B1 Class AB amplifier for use in semiconductor memory devices 有权
标题翻译： AB类放大器用于半导体存储器件
公开(公告)号：US06259280B1
公开(公告)日：2001-07-10
申请号：US09160844
申请日：1998-09-25
申请人： Jeffrey E. Koelling
发明人： Jeffrey E. Koelling
IPC分类号： G01R1900
CPC分类号： H03F3/3028 , H03F3/345 , H03F3/45264 , H03F3/45273
摘要： A class AB amplifier (400) is disclosed, having a first input node (402), a second input node (404), and an output node (406). A push-pull input stage (412) includes cross-coupled pairs of transistors, which form a charge current path and a discharge current path. When the voltage at the first input node (402) is greater than the voltage at the second input node (406), the amount of current drawn in the charge current path increases, and the amount of current drawn in the discharge current path decreases. When the voltage at the first input node (402) is less than the voltage at the second input node (404), the amount of current in the charge current path decreases while the amount of current in the discharge path increases. A first and fourth current mirror (422 and 428) are coupled to the charge current path, and a second and third current mirror (424 and 426) are coupled to the discharge current path. In response to increases in the amount of current drawn in the charge current path, the first current mirror (422) drives a discharge node (432) to a charge voltage, and the fourth current mirror (428) drives a charge node (434) to a charge voltage. In response to increases in the amount of current drawn in the discharge current path, the second current mirror (424) drives the discharge node (432) to discharge voltage, and the third current mirror (426) drives the charge node (434) to a discharge voltage. An output driver (430) charges the output node (406) when the charge node (434) is at the charge voltage, and discharges the output node (406) when the discharge node (432) is at the discharge voltage.
摘要翻译：公开了具有第一输入节点（402），第二输入节点（404）和输出节点（406）的AB类放大器（400）。推挽输入级（412）包括交叉耦合的晶体管对，其形成充电电流路径和放电电流路径。当第一输入节点（402）处的电压大于第二输入节点（406）处的电压时，在充电电流路径中拉出的电流量增加，并且在放电电流路径中吸取的电流量减小。当第一输入节点（402）处的电压小于第二输入节点（404）处的电压时，充电电流路径中的电流量减小，同时放电路径中的电流量增加。第一和第四电流镜（422和428）耦合到充电电流路径，并且第二和第三电流镜（424和426）耦合到放电电流路径。响应于在充电电流路径中的电流量的增加，第一电流镜422将放电节点（432）驱动到充电电压，并且第四电流镜428驱动充电节点（434）到充电电压。响应于在放电电流路径中吸入的电流量的增加，第二电流镜（424）驱动放电节点（432）放电电压，并且第三电流镜（426）将充电节点（434）驱动到放电电压。当充电节点（434）处于充电电压时，输出驱动器（430）对输出节点（406）充电，并且当放电节点（432）处于放电电压时，对输出节点（406）进行放电。

3. 发明授权

US6115321A Synchronous dynamic random access memory with four-bit data prefetch 失效
标题翻译：具有四位数据预取功能的同步动态随机存取存储器
公开(公告)号：US6115321A
公开(公告)日：2000-09-05
申请号：US110620
申请日：1998-07-06
申请人： Jeffrey E. Koelling , J. Patrick Kawamura
发明人： Jeffrey E. Koelling , J. Patrick Kawamura
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1072 , G11C7/1078
摘要： A memory circuit for operating synchronously with a system clock signal is designed with a memory array (250, 252, 254, 256) having a plurality of memory cells arranged in rows and columns. Each column decode circuit of a plurality of column decode circuits (502) produces a select signal at a respective column select line (108) in response to a first column address signal. A plurality of sense amplifier circuits (202) is arranged in groups. Each sense amplifier circuit is coupled to a respective column of memory cells. Each sense amplifier circuit includes a select transistor for coupling the sense amplifier to a respective data line (203). A control terminal of each select transistor of a group of sense amplifier circuits is connected to the respective column select line. A data sequence circuit (218) is coupled to receive four data bits from four respective data lines (210, 212, 214, 216) in response to a first cycle of the system clock signal. The data sequence circuit produces four ordered data bits in response to a control signal and a second column address signal. A register circuit (220) is coupled to receive the four ordered data bits. The register circuit produces a sequence of the four ordered data bits in response to a plurality of cycles of the system clock signal after the first cycle of the system clock signal.
摘要翻译：用于与系统时钟信号同步操作的存储器电路被设计为具有以行和列排列的多个存储器单元的存储器阵列（250,252,254,256）。响应于第一列地址信号，多列列解码电路（502）的每列解码电路在相应的列选择线（108）产生选择信号。多个读出放大器电路（202）分组布置。每个读出放大器电路耦合到相应的存储单元列。每个读出放大器电路包括用于将读出放大器耦合到相应的数据线（203）的选择晶体管。一组读出放大器电路的每个选择晶体管的控制端子连接到相应的列选择线。数据序列电路（218）被耦合以响应于系统时钟信号的第一周期从四个相应的数据线（210,212,214,216）接收四个数据位。数据序列电路响应于控制信号和第二列地址信号产生四个有序的数据位。寄存器电路（220）被耦合以接收四个有序的数据位。寄存器电路在系统时钟信号的第一周期之后响应于系统时钟信号的多个周期而产生四个有序数据位的序列。

4. 发明授权

US6069813A System with meshed power and signal buses on cell array 有权
公开(公告)号：US6069813A
公开(公告)日：2000-05-30
申请号：US330579
申请日：1999-06-11
申请人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
发明人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
IPC分类号： G11C11/401 , G11C5/02 , G11C5/14 , G11C7/06 , G11C7/18 , G11C8/14 , G11C11/34 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108 , G11C5/06
CPC分类号： G11C5/025 , G11C5/14 , G11C7/065 , G11C7/18 , G11C8/14
摘要： A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

5. 发明授权

US6005822A Bank selectable Y-decoder circuit and method of operation 有权
标题翻译：银行可选Y解码电路及其操作方法
公开(公告)号：US6005822A
公开(公告)日：1999-12-21
申请号：US209375
申请日：1998-12-10
申请人： Patrick J. Kawamura , Jeffrey E. Koelling
发明人： Patrick J. Kawamura , Jeffrey E. Koelling
IPC分类号： G11C11/413 , G11C7/10 , G11C8/10 , G11C8/12 , G11C11/401 , G11C11/407 , G11C8/00
CPC分类号： G11C7/1018 , G11C8/10 , G11C8/12
摘要： Bank selectable Y-decoder circuit (24) generates a plurality of Y-select signals (60, 62, 64, 66) for addressing columns of a plurality of memory banks (12, 14) in a memory array (10) and includes a high-order column factors decode circuit (34) for receiving a plurality of column factor signals. A first low-order column factor circuit (30) generates a first set of Y-select signals (60, 62) for addressing at least one column of a first set of memory banks (12). A second low-order column factors circuit (32) generates a second set of Y-select signals (64, 66) for addressing at least one column of a second set of memory banks (14). The result is a Y-decoder circuit (24) that consumes less silicon die area, without a reduction in circuit performance.
摘要翻译：存储体可选Y解码器电路（24）产生用于寻址存储器阵列（10）中的多个存储体（12,14）的列的多个Y选择信号（60,62,64,66），并且包括高阶列因素解码电路（34），用于接收多个列因子信号。第一低阶列因子电路（30）产生用于寻址第一组存储体（12）的至少一列的第一组Y选择信号（60,62）。第二低阶列因子电路（32）产生用于寻址第二组存储体（14）的至少一列的第二组Y选择信号（64,66）。结果是在不降低电路性能的情况下消耗较少硅芯片面积的Y解码器电路（24）。

6. 发明授权

US5945869A Voltage detector using body effect 失效
标题翻译：电压检测器采用身体效果
公开(公告)号：US5945869A
公开(公告)日：1999-08-31
申请号：US73930
申请日：1998-05-06
申请人： Jeffrey E. Koelling
发明人： Jeffrey E. Koelling
IPC分类号： G11C5/14 , H03K3/01
CPC分类号： G11C5/147 , G11C5/145
摘要： A circuit is designed with a first reference circuit (202) for producing a first reference voltage in response to a first voltage. A second reference circuit (204) produces a second reference voltage in response to the first voltage and a second voltage. A sampling circuit (210) stores the first reference voltage and the second reference voltage and produces a first sample voltage and a second sample voltage. A comparator circuit (222) is coupled to receive the first sample voltage and the second sample voltage. The comparator circuit produces a control signal in response to a difference between the first sample voltage and the second sample voltage. A generator circuit includes an oscillator circuit (226) and a pump circuit (230). The generator circuit produces a first supply voltage in response to the control signal.
摘要翻译：电路设计有第一参考电路（202），用于响应于第一电压产生第一参考电压。第二参考电路（204）响应于第一电压和第二电压产生第二参考电压。采样电路（210）存储第一参考电压和第二参考电压，并产生第一采样电压和第二采样电压。比较器电路（222）被耦合以接收第一采样电压和第二采样电压。比较器电路响应于第一采样电压和第二采样电压之间的差异产生控制信号。发电机电路包括振荡电路（226）和泵电路（230）。发生器电路响应于控制信号产生第一电源电压。

7. 发明授权

US06967371B2 System with meshed power and signal buses on cell array 失效
公开(公告)号：US06967371B2
公开(公告)日：2005-11-22
申请号：US10945351
申请日：2004-09-20
申请人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
发明人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
IPC分类号： G11C5/02 , G11C5/06 , G11C5/14 , G11C7/06 , G11C7/18 , G11C8/14 , H01L21/8242 , H01L23/528 , H01L27/108
CPC分类号： G11C5/063 , G11C5/025 , G11C5/14 , G11C7/065 , G11C7/18 , G11C8/14 , H01L23/5286 , H01L27/0207 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

8. 发明授权

US06297671B1 Level detection by voltage addition/subtraction 有权
公开(公告)号：US06297671B1
公开(公告)日：2001-10-02
申请号：US09383696
申请日：1999-08-26
申请人： Albert Shih , Jeffrey E. Koelling
发明人： Albert Shih , Jeffrey E. Koelling
IPC分类号： H03K522
CPC分类号： G06F1/26 , G11C5/143 , G11C11/4074 , G11C16/30 , H03K5/08
摘要： A circuit is designed with a first transistor (661) having a current path coupled between a supply terminal (32) and a first output terminal (665). A second transistor has a current path coupled between the first output terminal and a reference terminal. The current path of the second transistor current path has substantially the same width and length as the first transistor current path. A first comparator circuit (679, 685) has first (668) and second (23) input terminals and a second output terminal (681). The first input terminal is coupled to the first output terminal. The first comparator circuit produces a control signal in response to a voltage between the first and second input terminals. A generator circuit (80) receives the control signal and produces an output voltage at the supply terminal.

9. 发明授权

US06281760B1 On-chip temperature sensor and oscillator for reduced self-refresh current for dynamic random access memory 有权
标题翻译：用于动态随机存取存储器的片上温度传感器和振荡器，用于减少自刷新电流
公开(公告)号：US06281760B1
公开(公告)日：2001-08-28
申请号：US09356078
申请日：1999-07-16
申请人： Jeffrey E. Koelling , Wah Kit Loh
发明人： Jeffrey E. Koelling , Wah Kit Loh
IPC分类号： H03B524
CPC分类号： G11C11/406 , G11C7/04 , G11C11/40626 , H03K3/011 , H03K3/0315
摘要： A temperature dependent clock circuit (100) is disclosed. The clock circuit (100) includes a reference circuit (102) that provides a first group of reference signals (108) with positive temperature coefficients and a second group of reference signals (110) with negative temperature coefficients. A sample circuit (104) compares the first group of signals (108) with a second group of signals (110) and provides a group of bias signals (112) representative of the operating temperature of the clock circuit (100). A frequency controllable oscillator circuit (106) provides an output clock signal (CLK) having a frequency that is dependent upon the values of the bias signals (112).
摘要翻译：公开了一种与温度相关的时钟电路（100）。时钟电路（100）包括提供具有正温度系数的第一组参考信号（108）和具有负温度系数的第二组参考信号（110）的参考电路（102）。采样电路（104）将第一组信号（108）与第二组信号（110）进行比较，并提供代表时钟电路（100）的工作温度的一组偏置信号（112）。频率可控振荡器电路（106）提供具有取决于偏置信号（112）的值的频率的输出时钟信号（CLK）。

10. 发明授权

US5623448A Apparatus and method for implementing integrated circuit memory device component redundancy using dynamic power distribution switching 失效
标题翻译：使用动态功率分配切换实现集成电路存储器件组件冗余的装置和方法
公开(公告)号：US5623448A
公开(公告)日：1997-04-22
申请号：US437602
申请日：1995-05-09
申请人： Jeffrey E. Koelling
发明人： Jeffrey E. Koelling
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G11C13/00
CPC分类号： G11C29/84 , G11C29/832
摘要： In order to select between normal memory components and redundant memory components in an integrated circuit memory device, a logic signal (ENABLE/DISABLE) indicative of the requirement to access the normal memory components or to access the redundant memory components is generated in response to an applied address signal group. When the logic signal has a first logic state, power from dynamic power distribution unit (35) is applied to the output stages (32) of the column addressing apparatus (11,32) activating the normal column conducting paths and power is withheld from the output stages (37) which would otherwise activate the redundant column conducting paths. When the logic signal (ENABLE/DISABLE) has a second logic state, power is applied to the output stages 37 activating the redundant column conducting paths and withheld from the output stages 32 which would otherwise activate the normal column conducting paths. By directly controlling the power applied to the output stages (32,37), the logical combination of control signal and other parameter-bearing signals is avoided, thereby resulting in a faster response to the changes in the logic signal.
摘要翻译：为了在集成电路存储器件中的正常存储器组件和冗余存储器组件之间进行选择，响应于一个逻辑信号（ENABLE / DISABLE），指示访问正常存储器组件或访问冗余存储器组件的要求应用地址信号组。当逻辑信号具有第一逻辑状态时，来自动态功率分配单元（35）的功率被施加到激活正常列导通路径的列寻址设备（11,32）的输出级（32），并且从输出级（37），否则将激活冗余列传导路径。当逻辑信号（ENABLE / DISABLE）具有第二逻辑状态时，功率被施加到输出级37，激活冗余列传导路径，并从输出级32保留，否则将激活正常的列传导路径。通过直接控制施加到输出级（32,37）的功率，避免了控制信号和其他参数承载信号的逻辑组合，从而导致对逻辑信号的变化的更快响应。

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