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1. 发明申请

US20090080257A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090080257A1
公开(公告)日：2009-03-26
申请号：US12233580
申请日：2008-09-18
申请人： YASUSHI OKA , Tadashi Omae , Takesada Akiba
发明人： YASUSHI OKA , Tadashi Omae , Takesada Akiba
IPC分类号： G11C11/34
CPC分类号： G11C5/025 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.
摘要翻译：包括非易失性存储器的半导体器件的芯片面积减小。半导体器件包括形成在基板的主表面上并彼此相邻布置的第一存储单元和第二存储单元。在基板的主表面上布置有彼此电隔离的有源区。在第一有源区域中，布置第一存储单元的电容器元件，而第二存储单元的电容器元件布置在第四有源区域中。在第二有源区域中，布置有第一和第二存储单元的相应写/擦除元件。此外，在第三有源区域中，布置有第一和第二存储单元的各个读取元件。

2. 发明授权

US5847995A Nonvolatile semiconductor memory device having a plurality of blocks provided on a plurality of electrically isolated wells 失效
标题翻译：具有设置在多个电隔离的井上的多个块的非易失性半导体存储器件
公开(公告)号：US5847995A
公开(公告)日：1998-12-08
申请号：US852354
申请日：1997-05-07
申请人： Shinichi Kobayashi , Shinji Kawai , Tadashi Omae , Makoto Oi , Akinori Matsuo , Masashi Wada , Kenji Kozakai
发明人： Shinichi Kobayashi , Shinji Kawai , Tadashi Omae , Makoto Oi , Akinori Matsuo , Masashi Wada , Kenji Kozakai
IPC分类号： G11C17/00 , G11C16/06 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/78
摘要： The inventive DINOR flash memory includes a plurality of blocks, a spare block and a spare word line block, which are formed on a plurality of electrically isolated P-type wells. When a word line-to-well short-circuit takes place in a certain block and another block is selected, the block causing the word line-to-well short-circuit is brought into a non-selected state. Thus, no leakage takes place in the block causing the word line-to-well short-circuit, to exert no bad influence on the selected block.
摘要翻译：本发明的DINOR闪速存储器包括形成在多个电隔离P型阱上的多个块，备用块和备用字线块。当在某个块中发生字线对阱短路并且选择另一个块时，导致字线对阱短路的块被带入非选择状态。因此，在导致字线到阱短路的块中不发生泄漏，对所选择的块不会产生不良影响。

3. 发明授权

US08325524B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08325524B2
公开(公告)日：2012-12-04
申请号：US12903774
申请日：2010-10-13
申请人： Yasushi Oka , Tadashi Omae , Takesada Akiba
发明人： Yasushi Oka , Tadashi Omae , Takesada Akiba
IPC分类号： G11C14/00
CPC分类号： G11C5/025 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.
摘要翻译：包括非易失性存储器的半导体器件的芯片面积减小。半导体器件包括形成在基板的主表面上并彼此相邻布置的第一存储单元和第二存储单元。在基板的主表面上布置有彼此电隔离的有源区。在第一有源区域中，布置第一存储单元的电容器元件，而第二存储单元的电容器元件布置在第四有源区域中。在第二有源区域中，布置有第一和第二存储单元的相应写/擦除元件。此外，在第三有源区域中，布置有第一和第二存储单元的各个读取元件。

4. 发明申请

US20110024814A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20110024814A1
公开(公告)日：2011-02-03
申请号：US12903774
申请日：2010-10-13
申请人： Yasushi OKA , Tadashi Omae , Takesada Akiba
发明人： Yasushi OKA , Tadashi Omae , Takesada Akiba
IPC分类号： H01L27/108
CPC分类号： G11C5/025 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.
摘要翻译：包括非易失性存储器的半导体器件的芯片面积减小。半导体器件包括形成在基板的主表面上并彼此相邻布置的第一存储单元和第二存储单元。在基板的主表面上布置有彼此电隔离的有源区。在第一有源区域中，布置第一存储单元的电容器元件，而第二存储单元的电容器元件布置在第四有源区域中。在第二有源区域中，布置有第一和第二存储单元的相应写/擦除元件。此外，在第三有源区域中，布置有第一和第二存储单元的各个读取元件。

5. 发明授权

US07839683B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07839683B2
公开(公告)日：2010-11-23
申请号：US12233580
申请日：2008-09-18
申请人： Yasushi Oka , Tadashi Omae , Takesada Akiba
发明人： Yasushi Oka , Tadashi Omae , Takesada Akiba
IPC分类号： G11C14/00
CPC分类号： G11C5/025 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.
摘要翻译：包括非易失性存储器的半导体器件的芯片面积减小。半导体器件包括形成在基板的主表面上并彼此相邻布置的第一存储单元和第二存储单元。在基板的主表面上布置有彼此电隔离的有源区。在第一有源区域中，布置第一存储单元的电容器元件，而第二存储单元的电容器元件布置在第四有源区域中。在第二有源区域中，布置有第一和第二存储单元的相应写/擦除元件。此外，在第三有源区域中，布置有第一和第二存储单元的各个读取元件。

6. 发明授权

US06660586B2 Semiconductor device and process for manufacturing same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US06660586B2
公开(公告)日：2003-12-09
申请号：US10096488
申请日：2002-03-13
申请人： Ippei Shimizu , Satoshi Shimizu , Tadashi Omae
发明人： Ippei Shimizu , Satoshi Shimizu , Tadashi Omae
IPC分类号： H01L218234
CPC分类号： H01L21/32155
摘要： A process for manufacturing a semiconductor device includes the following steps applied to a semiconductor substrate having, on its main surface, a plurality of separation oxide films, formed in stripes parallel to each other, and gate oxide films formed in the regions placed between separation oxide films, wherein pieces of a polysilicon layer are formed so as to extend from areas above gate oxide films to areas above portions of separation oxide films on both sides of the gate oxide films and wherein a first resist is formed so as to cover the top surfaces of polysilicon layer: the injection step of injecting an impurity into polysilicon layer above separation oxide films; and the thermal diffusion step of carrying out a heat processing so that the injected impurity diffuses to the regions above gate oxide films within polysilicon layer.
摘要翻译：一种半导体器件的制造方法，其特征在于，在半导体基板的主表面上形成有以彼此平行的条状形成的多个分离氧化膜以及形成在分离氧化物膜，其中形成多个多晶硅层，以便从栅极氧化膜上方的区域延伸到栅极氧化膜两侧的分离氧化膜部分上方的区域，并且其中形成第一抗蚀剂以覆盖顶表面的多晶硅层：将杂质注入分离氧化膜上方的多晶硅层的注入工序; 以及进行热处理使得注入的杂质扩散到多晶硅层内的栅极氧化膜上方的区域的热扩散步骤。

7. 发明授权

US06414393B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06414393B2
公开(公告)日：2002-07-02
申请号：US09739766
申请日：2000-12-20
申请人： Jun Sumino , Tadashi Omae , Satoshi Shimizu
发明人： Jun Sumino , Tadashi Omae , Satoshi Shimizu
IPC分类号： H01L2348
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a semiconductor device having a multilayer wiring structure in which a plurality of layers are provided on a substrate and in which a connection wiring is formed on each layer, wherein a dummy pattern almost as high as the connection wiring is provided in a predetermined region of each layer so that an outer peripheral portion of the dummy pattern is adjacent to the connection wiring, the dummy pattern is formed linearly at least on the outer peripheral portion, and a distance between a linearly formed portion and a portion inside of the linearly formed portion is set to be equal to or narrower than a distance between the connection wiring and the linearly formed portion.
摘要翻译：本发明提供一种具有多层布线结构的半导体器件，其中多个层设置在基片上，并且其中在每个层上形成连接布线，其中以与连接布线几乎相同的虚拟图案设置在预定的区域，使得虚设图案的外周部分与连接布线相邻，虚设图案至少在外周部分线性地形成，并且线性形成部分与线性部分内部之间的距离形成部分被设定为等于或窄于连接布线和直线形成部分之间的距离。

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