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1. 发明申请

US20110024814A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20110024814A1
公开(公告)日：2011-02-03
申请号：US12903774
申请日：2010-10-13
申请人： Yasushi OKA , Tadashi Omae , Takesada Akiba
发明人： Yasushi OKA , Tadashi Omae , Takesada Akiba
IPC分类号： H01L27/108
CPC分类号： G11C5/025 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.
摘要翻译：包括非易失性存储器的半导体器件的芯片面积减小。半导体器件包括形成在基板的主表面上并彼此相邻布置的第一存储单元和第二存储单元。在基板的主表面上布置有彼此电隔离的有源区。在第一有源区域中，布置第一存储单元的电容器元件，而第二存储单元的电容器元件布置在第四有源区域中。在第二有源区域中，布置有第一和第二存储单元的相应写/擦除元件。此外，在第三有源区域中，布置有第一和第二存储单元的各个读取元件。

2. 发明申请

US20110233639A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110233639A1
公开(公告)日：2011-09-29
申请号：US13046751
申请日：2011-03-13
申请人： Hideaki YAMAKOSHI , Yasushi OKA , Daisuke OKADA
发明人： Hideaki YAMAKOSHI , Yasushi OKA , Daisuke OKADA
IPC分类号： H01L29/788
CPC分类号： G11C16/0441 , G11C5/06 , G11C16/0433 , H01L27/11519 , H01L27/11521
摘要： To improve performance of a semiconductor device having a nonvolatile memory. Further to improve reliability of the semiconductor device. Furthermore, to improve performance of a semiconductor device as well as improving reliability of the semiconductor device.A plurality of memory cells each configured by a memory transistor having a floating gate and a control transistor coupled in series to the memory transistor is arranged in an array in an X direction and in a Y direction on the main surface of a semiconductor substrate. Then, a bit wire that couples drain regions of the memory transistors of the memory cells arranged in the X direction is provided in the lowermost wiring layer of a multilayer wiring structure formed over the semiconductor substrate and the bit wire is arranged to cover the whole floating gate electrode.
摘要翻译：为了提高具有非易失性存储器的半导体器件的性能。进一步提高半导体器件的可靠性。此外，为了提高半导体器件的性能以及提高半导体器件的可靠性。每个由具有浮动栅极和与存储晶体管串联耦合的控制晶体管的存储晶体管构成的多个存储单元在半导体衬底的主表面上沿X方向和Y方向排列。然后，在形成在半导体衬底上的多层布线结构的最下层布线层中设置有将在X方向排列的存储单元的存储晶体管的漏极区域连接的位线，并且位线布置成覆盖整个浮置栅电极。

3. 发明申请

US20100038693A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100038693A1
公开(公告)日：2010-02-18
申请号：US12603332
申请日：2009-10-21
申请人： Kazuyoshi SHIBA , Yasushi OKA
发明人： Kazuyoshi SHIBA , Yasushi OKA
IPC分类号： H01L29/94
CPC分类号： H01L27/11558 , G11C16/0441 , H01L27/0207 , H01L27/0629 , H01L27/105 , H01L27/11519 , H01L27/11521 , H01L27/11526
摘要： p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.
摘要翻译： p型阱设置在位于形成闪存的区域中的半导体衬底的n型嵌入阱中，处于彼此隔离的状态。电容部分，数据写入/擦除电荷注入/放电部分和数据读取MIS·FET被设置在每个p型阱中。电容部分设置在数据写入/擦除电荷注入/放电部分和数据读取MIS•FET之间。在数据写入/擦除电荷注入/放电部分中，执行通道整个表面处的FN隧道电流的数据写入和擦除。

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