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31. 发明申请

US20080149021A1 Methods of Forming Dual Damascene Structures 失效
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US20080149021A1
公开(公告)日：2008-06-26
申请号：US12043576
申请日：2008-03-06
申请人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
发明人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
IPC分类号： C30B25/02
CPC分类号： H01L21/76876 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02645 , H01L21/28525 , H01L21/28562 , H01L21/76808 , H01L21/76831 , H01L21/76879 , H01L21/76895 , H01L29/66477 , Y10T428/24331
摘要： A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.
摘要翻译：公开了一种双镶嵌结构和形成双镶嵌结构的方法。双镶嵌结构包括绝缘构件，单晶构件和填充构件。绝缘构件具有双镶嵌形状的开口。填充构件形成在开口的侧面上。单晶构件接触填充构件。单晶构件填充开口。为了形成双镶嵌结构，形成具有部分填充有初级单晶构件的开口的绝缘构件。填充构件形成在开口的侧面上。外延的初步单晶构件生长以填满开口。由于填充构件位于单晶构件和绝缘构件之间，所以在单晶构件和绝缘构件之间可能会减小空隙形成。

32. 发明申请

US20070254394A1 Gallium nitride-based light emitting device having ESD protection capacity and method for manufacturing the same 失效
公开(公告)号：US20070254394A1
公开(公告)日：2007-11-01
申请号：US11812868
申请日：2007-06-22
申请人： Jun Seo , Suk Yoon , Seung Chae
发明人： Jun Seo , Suk Yoon , Seung Chae
IPC分类号： H01L21/00
CPC分类号： H01L33/04 , H01L27/0248 , H01L27/15 , H01L33/32 , H01L33/38 , H01L33/44 , H01L2933/0016
摘要： A gallium nitride-based light emitting device, and a method for manufacturing the same are disclosed. The light emitting device comprises an n-type GaN-based clad layer, an active layer, a p-type GaN-based clad layer and a p-side electrode sequentially stacked on a substrate. The device further comprises an n-side electrode formed on one region of the n-type GaN-based clad layer, and two or more MIM type tunnel junctions formed on the other regions of the n-type GaN-based clad layer. Each of the MIM type tunnel junctions comprises a lower metal layer formed on the GaN-based clad layer so as to contact the n-type GaN-based clad layer, an insulating film formed on the lower metal layer, and an upper metal layer formed on the insulating film. The device is protected from reverse ESD voltage, so that tolerance to reverse ESD voltage can be enhanced, thereby improving reliability of the device.

33. 发明申请

US20060157718A1 Gallium nitride-based light emitting device having ESD protection capacity and method for manufacturing the same 有权
标题翻译：具有ESD保护能力的氮化镓系发光器件及其制造方法
公开(公告)号：US20060157718A1
公开(公告)日：2006-07-20
申请号：US11220844
申请日：2005-09-08
申请人： Jun Seo , Suk Yoon , Seung Chae
发明人： Jun Seo , Suk Yoon , Seung Chae
IPC分类号： H01L31/12 , H01L27/15
CPC分类号： H01L33/04 , H01L27/0248 , H01L27/15 , H01L33/32 , H01L33/38 , H01L33/44 , H01L2933/0016
摘要： A gallium nitride-based light emitting device, and a method for manufacturing the same are disclosed. The light emitting device comprises an n-type GaN-based clad layer, an active layer, a p-type GaN-based clad layer and a p-side electrode sequentially stacked on a substrate. The device further comprises an n-side electrode formed on one region of the n-type GaN-based clad layer, and two or more MIM type tunnel junctions formed on the other regions of the n-type GaN-based clad layer. Each of the MIM type tunnel junctions comprises a lower metal layer formed on the GaN-based clad layer so as to contact the n-type GaN-based clad layer, an insulating film formed on the lower metal layer, and an upper metal layer formed on the insulating film. The device is protected from reverse ESD voltage, so that tolerance to reverse ESD voltage can be enhanced, thereby improving reliability of the device.
摘要翻译：公开了一种氮化镓基发光器件及其制造方法。发光器件包括依次层叠在衬底上的n型GaN基覆盖层，有源层，p型GaN基覆盖层和p侧电极。该器件还包括形成在n型GaN基覆盖层的一个区域上的n侧电极和形成在n型GaN基覆盖层的其它区域上的两个或更多个MIM型隧道结。每个MIM型隧道结包括形成在GaN基覆层上的下金属层，以便接触n型GaN基覆层，形成在下金属层上的绝缘膜和形成的上金属层在绝缘膜上。该器件可防止反向ESD电压，从而可以提高对反向ESD电压的容限，从而提高器件的可靠性。

34. 发明申请

US20050133796A1 Nitride semiconductor light emitting diode and fabrication method thereof 有权
标题翻译：氮化物半导体发光二极管及其制造方法
公开(公告)号：US20050133796A1
公开(公告)日：2005-06-23
申请号：US10870467
申请日：2004-06-18
申请人： Jun Seo , Jong Jang
发明人： Jun Seo , Jong Jang
IPC分类号： H01L27/15 , H01L33/06 , H01L33/10 , H01L33/32 , H01L33/46 , H01L33/62
CPC分类号： H01L33/46 , H01L2224/48091 , H01L2224/49107 , H01L2224/73265 , Y10S257/918 , H01L2924/00014
摘要： The invention relates to a nitride semiconductor LED and a fabrication method thereof. In the LED, a first nitride semiconductor layer, an active region a second nitride semiconductor layer of a light emitting structure are formed in their order on a transparent substrate. A dielectric mirror layer is formed on the underside of the substrate, and has at least a pair of alternating first dielectric film of a first refractivity and a second dielectric film of a second refractivity larger than the first refractivity. A lateral insulation layer is formed on the side of the substrate and the light emitting structure. The LED of the invention effectively collimate undesirably-directed light rays, which may be otherwise extinguished, to maximize luminous efficiency, and are protected by the dielectric mirror layer formed on the side thereof to remarkably improve ESD characteristics.
摘要翻译：本发明涉及一种氮化物半导体LED及其制造方法。在LED中，第一氮化物半导体层，有源区，发光结构的第二氮化物半导体层依次形成在透明基板上。电介质镜层形成在衬底的下侧，并且具有至少一对第一折射率的交替的第一介电膜和具有大于第一折射率的第二折射率的第二电介质膜。在基板和发光结构的侧面上形成横向绝缘层。本发明的LED有效地准直了可能被熄灭的不期望的导向的光线，以使发光效率最大化，并且被形成在其侧面上的电介质镜层保护以显着改善ESD特性。

35. 发明申请

US20050042833A1 Method of manufacturing integrated circuit device including recessed channel transistor 失效
标题翻译：集成电路器件制造方法，包括凹陷沟道晶体管
公开(公告)号：US20050042833A1
公开(公告)日：2005-02-24
申请号：US10902642
申请日：2004-07-28
申请人： Jong-Chul Park , Jun Seo , Tae-Hyuk Ahn , Hyuk-Jin Kwon , Jong-Heui Song , Dae-Keun Kang
发明人： Jong-Chul Park , Jun Seo , Tae-Hyuk Ahn , Hyuk-Jin Kwon , Jong-Heui Song , Dae-Keun Kang
IPC分类号： H01L21/336 , H01L21/4763 , H01L29/78
CPC分类号： H01L29/66553 , H01L29/66621 , H01L29/7834
摘要： A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.
摘要翻译：根据本发明的一些实施例的方法包括通过在集成衬底上形成沟槽器件隔离区域来限定有源区域，形成掩模图案，其暴露有源区域的沟道子区域和与该区域相邻的沟槽器件隔离区域使用掩模图案作为蚀刻掩模蚀刻由掩模图案曝光的沟槽器件隔离区域，以凹陷到第一深度，蚀刻沟道子区域以形成栅极沟槽，栅极沟道具有第二深度比使用掩模图案的第一深度深的蚀刻掩模，以及形成填充栅极沟槽的凹槽。

36. 发明授权

US06239022B1 Method of fabricating a contact in a semiconductor device 有权
标题翻译：在半导体器件中制造接触的方法
公开(公告)号：US06239022B1
公开(公告)日：2001-05-29
申请号：US09604708
申请日：2000-06-27
申请人： Jun Seo , Woo-Sik Kim , Jong-Heui Song , Young-Woo Park
发明人： Jun Seo , Woo-Sik Kim , Jong-Heui Song , Young-Woo Park
IPC分类号： H01L214763
CPC分类号： H01L21/76885 , H01L21/31116 , H01L21/32137 , H01L21/7684
摘要： A method for forming a contact plug formed of polysilicon and a method for manufacturing a semiconductor device using the same are provided. The contact plug is formed by etching back polysilicon which fills a contact hole and is deposited on an interlayer dielectric film using a gas mixture of SF6, CHF3, and CF4, thus planarizing the polysilicon. Also, the contact plug can be made protrude above the interlayer dielectric film by etching the entire surface of the exposed interlayer dielectric film around the polysilicon contact plug formed by etching back the polysilicon. According to the present invention, the degree of planarization of the polysilicon contact plug is improved by etching back the polysilicon using the gas mixture of SF6, CHF3, and CF4. Furthermore, it is possible to prevent contact failure due to the depression of the contact plug by etching the entire surface of the interlayer dielectric film thus causing the contact plug to protrude above the interlayer dielectric film, thereby increasing the plug's contact area and reducing the contact failure.
摘要翻译：提供一种用于形成由多晶硅形成的接触插塞的方法以及使用其形成半导体器件的方法。接触插塞是通过将填充接触孔的多晶硅蚀刻回来形成的，并且使用SF6，CHF3和CF4的气体混合物沉积在层间电介质膜上，从而平坦化多晶硅。此外，通过蚀刻暴露的层间电介质膜的整个表面，接触插塞可以突出在层间电介质膜的上方，通过蚀刻多晶硅而形成的多晶硅接触插塞周围。根据本发明，通过使用SF6，CHF3和CF4的气体混合物蚀刻多晶硅来提高多晶硅接触插塞的平坦化程度。此外，可以通过蚀刻层间电介质膜的整个表面来防止接触插塞的接触故障，从而使接触插塞突出到层间电介质膜之上，从而增加插头的接触面积并减少接触失败。

37. 发明授权

US08378395B2 Methods of fabricating field effect transistors having protruded active regions 有权
标题翻译：制造具有突出的活性区域的场效应晶体管的方法
公开(公告)号：US08378395B2
公开(公告)日：2013-02-19
申请号：US12977811
申请日：2010-12-23
申请人： Ji-Young Lee , Jun Seo
发明人： Ji-Young Lee , Jun Seo
IPC分类号： H01L29/78
CPC分类号： H01L29/1037 , H01L21/76229 , H01L27/105 , H01L29/66621 , H01L29/7834
摘要： Provided are a field effect transistor, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor may have a structure in which a double gate field effect transistor and a recess channel array transistor are formed in a single transistor in order to improve a short channel effect which occurs as field effect transistors become more highly integrated, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor can exhibit stable device characteristics even when more highly integrated in such a manner that both the length and width of a channel increase and particularly the channel can be significantly long, and can be manufactured simply.
摘要翻译：提供了场效应晶体管，其制造方法以及包括场效应晶体管的电子器件。场效应晶体管可以具有在单个晶体管中形成双栅极场效应晶体管和凹槽沟道阵列晶体管的结构，以便改善随着场效应晶体管变得更高度集成而发生的短沟道效应，制造它们，以及包括场效应晶体管的电子器件。即使当以通道的长度和宽度都增加并且特别是通道可以显着长的方式更高度集成时，场效应晶体管也可以表现出稳定的器件特性，并且可以简单地制造。

38. 发明授权

US07929341B2 Electromechanical switch and method of forming the same 有权
标题翻译：机电开关及其形成方法
公开(公告)号：US07929341B2
公开(公告)日：2011-04-19
申请号：US12392780
申请日：2009-02-25
申请人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Weonwi Jang , Keun-Hwi Cho
发明人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Weonwi Jang , Keun-Hwi Cho
IPC分类号： G11C11/50
CPC分类号： H01L28/40 , H01L27/10894
摘要： A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.
摘要翻译：存储装置包括存储节点，第一电极和形成在存储单元中的第二电极，所述存储节点存储电荷，所述第一电极包括电连接到第二部分的第一部分，所述第一部分移动以连接到当第二电极通电时的存储节点。

39. 发明申请

US20100093167A1 Methods of Fabricating Field Effect Transistors Having Protruded Active Regions 有权
标题翻译：制造具有突出活动区域的场效应晶体管的方法
公开(公告)号：US20100093167A1
公开(公告)日：2010-04-15
申请号：US12639118
申请日：2009-12-16
申请人： Ji-Young Lee , Jun Seo
发明人： Ji-Young Lee , Jun Seo
IPC分类号： H01L21/336
CPC分类号： H01L29/1037 , H01L21/76229 , H01L27/105 , H01L29/66621 , H01L29/7834
摘要： Provided are a field effect transistor, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor may have a structure in which a double gate field effect transistor and a recess channel array transistor are formed in a single transistor in order to improve a short channel effect which occurs as field effect transistors become more highly integrated, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor can exhibit stable device characteristics even when more highly integrated in such a manner that both the length and width of a channel increase and particularly the channel can be significantly long, and can be manufactured simply.
摘要翻译：提供了场效应晶体管，其制造方法以及包括场效应晶体管的电子器件。场效应晶体管可以具有在单个晶体管中形成双栅极场效应晶体管和凹槽沟道阵列晶体管的结构，以便改善随着场效应晶体管变得更高度集成而发生的短沟道效应，制造它们，以及包括场效应晶体管的电子器件。即使当以通道的长度和宽度都增加并且特别是通道可以显着长的方式更高度集成时，场效应晶体管也可以表现出稳定的器件特性，并且可以简单地制造。

40. 发明申请

US20090321816A1 Vertical-type non-volatile memory device 审中-公开
标题翻译：垂直型非易失性存储器件
公开(公告)号：US20090321816A1
公开(公告)日：2009-12-31
申请号：US12459148
申请日：2009-06-26
申请人： Yong-Hoon Son , Jong-Wook Lee , Jun Seo , Jong-Hyuk Kang
发明人： Yong-Hoon Son , Jong-Wook Lee , Jun Seo , Jong-Hyuk Kang
IPC分类号： H01L29/792 , H01L27/088
CPC分类号： H01L27/11551 , H01L27/11556
摘要： In a vertical-type non-volatile memory device, first and second single-crystalline semiconductor pillars are arranged to face each other on a substrate. Each of the first and second single-crystalline semiconductor pillars has a rectangular parallelepiped shape with first, second, third and fourth sidewalls. A first tunnel oxide layer, a first charge storage layer and a first blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the first single-crystalline semiconductor pillar. A second tunnel oxide layer, a second charge storage layer and a second blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the second single-crystalline semiconductor pillar. A word line makes contact with surfaces of both the first and second blocking dielectric layers. The word line is used in common for the first and second single-crystalline semiconductor pillars.
摘要翻译：在垂直型非易失性存储器件中，第一和第二单晶半导体柱被布置成在衬底上彼此面对。第一和第二单晶半导体柱中的每一个具有与第一，第二，第三和第四侧壁的长方体形状。第一隧道氧化物层，第一电荷存储层和第一阻挡介电层依次层叠在第一单晶半导体柱的第一侧壁的整个表面上。第二隧道氧化物层，第二电荷存储层和第二阻挡电介质层依次层叠在第二单晶半导体柱的第一侧壁的整个表面上。字线与第一和第二阻挡电介质层的表面接触。字线用于第一和第二单晶半导体柱。

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