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31. 发明授权

US6025234A Method for manufacturing thick gate oxide device 失效
标题翻译：厚栅极氧化器件的制造方法
公开(公告)号：US6025234A
公开(公告)日：2000-02-15
申请号：US992675
申请日：1997-12-17
申请人： Jih-Wen Chou
发明人： Jih-Wen Chou
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823462 , Y10S438/931
摘要： A method for forming devices having a thick gate oxide. The method comprises the steps of providing a substrate having different device areas already defined thereon through shallow trench isolation, then forming a first gate oxide layer over the substrate. Next, a silicon nitride layer is formed over the first gate oxide layer, then patterned using a mask to selectively expose the first gate oxide layer in the thick gate oxide area. Subsequently, a thermal oxidation is performed to directly grow an oxide layer over the first gate oxide layer to form a thicker second gate oxide layer. Since no gate oxide layer is removed in this invention, the distribution of ions implanted in previous processing steps will remain unchanged. Therefore, the fabricated devices will have more stable properties and better reliability.
摘要翻译：一种用于形成具有厚栅极氧化物的器件的方法。该方法包括以下步骤：通过浅沟槽隔离提供具有已经在其上定义的不同器件区域的衬底，然后在衬底上形成第一栅极氧化物层。接下来，在第一栅极氧化物层上形成氮化硅层，然后使用掩模进行图案化以选择性地暴露厚栅极氧化物区域中的第一栅极氧化物层。随后，进行热氧化以在第一栅极氧化物层上直接生长氧化物层，以形成较厚的第二栅极氧化物层。由于在本发明中没有去除栅极氧化物层，所以在先前的处理步骤中植入的离子的分布将保持不变。因此，制造的器件将具有更稳定的性能和更好的可靠性。

32. 发明授权

US5914519A Air-gap spacer of a metal-oxide-semiconductor device 失效
标题翻译：金属氧化物半导体器件的气隙间隔物
公开(公告)号：US5914519A
公开(公告)日：1999-06-22
申请号：US9302
申请日：1998-01-20
申请人： Jih-Wen Chou , Tony Lin
发明人： Jih-Wen Chou , Tony Lin
IPC分类号： H01L21/336 , H01L29/49 , H01L29/78 , H01L29/14 , H01L29/76
CPC分类号： H01L29/66598 , H01L29/4983 , H01L29/4991 , H01L29/6659 , H01L29/7833
摘要： An air-gap spacer of a metal-oxide-semiconductor device comprises a spacer and a cross-sectional L-shaped air-gap. The spacer is adjacent to a sidewall of the gate electrode but not directly contacts to the gate electrode. The cross-sectional L-shaped air-gap is located between the spacer and the gate electrode and between the spacer and the substrate so that the spacer is separated from the gate electrode and the spacer is partially separated from the substrate.
摘要翻译：金属氧化物半导体器件的气隙间隔件包括间隔件和截面L形气隙。间隔物与栅电极的侧壁相邻，但不直接接触栅电极。横截面的L形气隙位于间隔件和栅电极之间，并且位于间隔件和衬底之间，使得间隔件与栅电极分离，并且间隔件与衬底部分地分离。

33. 发明授权

US5891783A Method of reducing fringe capacitance 失效
标题翻译：降低边缘电容的方法
公开(公告)号：US5891783A
公开(公告)日：1999-04-06
申请号：US927323
申请日：1997-09-11
申请人： Chih-Hung Lin , Jih-Wen Chou
发明人： Chih-Hung Lin , Jih-Wen Chou
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66583 , H01L21/28114 , H01L29/42376 , H01L29/4983 , H01L29/4991 , H01L29/7833
摘要： A method of reducing the fringe capacitance between a gate and a substrate in a semiconductor device. A silicon nitride is formed over a substrate with a buffer oxide layer thereon and patterned to form an opening. The buffer oxide layer within the opening is removed and another oxide layer is formed at the same place as a gate oxide layer. A poly-gate is formed at the opening with a wider width than the opening. Thus, a part of the poly-gate at both ends covers a part of the silicon nitride layer. The silicon nitride layer is then removed and leaves the poly-gate as a T-shape with two ends suspended over the substrate. With a large angle, a light dopant is implanted into the substrate under the suspended part of the poly-gate to form a lightly doped region. With another smaller angle, a heavy dopant is implanted into the substrate beside the poly-gate. Therefore, a source/drain is formed. A undoped silicate glass layer and a borophosphosilicate layer are formed in sequence, and an air gap is formed between the suspended part of the poly-gate and the substrate.
摘要翻译：一种降低半导体器件中栅极和衬底之间的条纹电容的方法。在其上具有缓冲氧化物层的衬底上形成氮化硅并且被图案化以形成开口。去除开口内的缓冲氧化物层，并且在与栅极氧化物层相同的位置处形成另一氧化物层。在开口处形成具有比开口宽的宽度的多门。因此，两端的多晶硅栅极的一部分覆盖氮化硅层的一部分。然后去除氮化硅层，并将多晶硅栅极留作T形，其两端悬在衬底上。以大角度，将光掺杂剂注入到多晶硅栅极的悬置部分之下的衬底中以形成轻掺杂区域。在另一个更小的角度，重掺杂剂被注入到多晶硅栅极旁边的衬底中。因此，形成源极/漏极。依次形成未掺杂的硅酸盐玻璃层和硼磷硅酸盐层，并且在多晶硅的悬浮部分和基板之间形成气隙。

34. 发明授权

US5843824A Diode-based semiconductor read-only memory device and method of fabricating the same 失效
标题翻译：基于二极管的半导体只读存储器件及其制造方法
公开(公告)号：US5843824A
公开(公告)日：1998-12-01
申请号：US838152
申请日：1997-04-15
申请人： Jih-Wen Chou , Jemmy Wen
发明人： Jih-Wen Chou , Jemmy Wen
IPC分类号： H01L21/8229 , H01L27/102 , H01L21/8236
CPC分类号： H01L27/1021 , H01L21/8229
摘要： A diode-based ROM device and a method for fabricating the same are provided. The ROM device is of the type including an array of diode-based memory cells for permanent storage of binary-coded data therein. In the semiconductor structure of the ROM device, a plurality of insulator-filled trenches are formed for isolation of the diode-based memory cells. This feature allows the prevention of the punch-through effect when the ROM device is downsized. Further, the bit lines for the ROM device are formed with an increased junction depth such that the resistance of the bit lines can be reduced to allow an increase in the magnitude of the currents in the bit lines for easier detection and distinguishing of the binary state the currents represent. In accordance with the method, the mask-programming process can be easily implemented by forming contact windows at predetermined locations that are associated with the memory cells that are to be set to a permanently-ON state, and then doping an impurity material through the contact windows into an upper portion of the associated bit lines to form a junction diode thereon. The memory cells that are not formed with diodes are set to a permanently-OFF state.
摘要翻译：提供一种基于二极管的ROM器件及其制造方法。 ROM器件的类型包括用于在其中永久存储二进制编码数据的基于二极管的存储器单元的阵列。在ROM器件的半导体结构中，形成多个绝缘体填充的沟槽，用于隔离二极管的存储单元。该功能允许当ROM设备缩小时防止穿透效果。此外，ROM器件的位线形成为具有增加的结深度，使得可以减小位线的电阻以允许位线中的电流的大小增加，以便于检测和区分二进制状态电流代表。根据该方法，可以通过在与要设置为永久导通状态的存储器单元相关联的预定位置处形成接触窗口，然后通过触点掺杂杂质材料来容易地实现掩模编程过程窗口进入相关位线的上部，以在其上形成结二极管。未形成二极管的存储单元被设置为永久关闭状态。

35. 发明授权

US5770508A Method of forming lightly doped drains in metalic oxide semiconductor components 失效
标题翻译：在金属氧化物半导体部件中形成轻掺杂漏极的方法
公开(公告)号：US5770508A
公开(公告)日：1998-06-23
申请号：US868816
申请日：1997-06-04
申请人： Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66598 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention relates to a method of forming lightly doped drains in metallic oxide semiconductor (MOS) components. The method includes forming a first, second, and third insulating layer above a silicon substrate having a gate, etching back the layers to leave behind L-shaped first spacers on sidewalls of the gate, followed by doping second type ions into the silicon substrate to form first lightly doped drains in the silicon substrate surface below the L-shaped first spacers, and second lightly doped drains in the silicon substrate surface elsewhere, further forming a fourth insulating to form third spacers, and using the using the third spacers, the first insulating layer, and the gate as masks when doping second type ions into the silicon substrate so as to form source/drain regions in silicon substrate surfaces not covered by the third spacers. Such a method produces greater yield and reduces leakage current from the transistor components.
摘要翻译：本发明涉及一种在金属氧化物半导体（MOS）部件中形成轻掺杂漏极的方法。该方法包括在具有栅极的硅衬底之上形成第一绝缘层，第二绝缘层和第三绝缘层，蚀刻层以留下栅极侧壁上的L形第一间隔物，然后将第二类型离子掺杂到硅衬底中在L基第一间隔物下面的硅衬底表面中形成第一轻掺杂漏极，在其他地方在硅衬底表面中形成第二轻掺杂漏极，进一步形成第四绝缘体以形成第三间隔物，并且使用第三间隔物，绝缘层和栅极作为掩模，当将第二类型离子掺入硅衬底中时，以便在未被第三间隔物覆盖的硅衬底表面中形成源/漏区。这种方法产生更大的产量并减少来自晶体管部件的泄漏电流。

36. 发明申请

US20050030789A1 METHOD FOR OPERATING A NAND-ARRAY MEMORY MODULE COMPOSED OF P-TYPE MEMORY CELLS 有权
标题翻译：用于操作由P型存储器单元组成的NAND阵列存储器模块的方法
公开(公告)号：US20050030789A1
公开(公告)日：2005-02-10
申请号：US10707562
申请日：2003-12-22
申请人： Ching-Hsiang Hsu , Ching-Sung Yang , Jih-Wen Chou , Cheng-Tung Huang , Chih-Hsun Chu
发明人： Ching-Hsiang Hsu , Ching-Sung Yang , Jih-Wen Chou , Cheng-Tung Huang , Chih-Hsun Chu
IPC分类号： G11C16/02 , G11C11/34 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475
摘要： A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the first transmission line of the column of the memory cell, turning off the P-type channel of at least one memory cell between the memory cell and the second transmission line of the column of the memory cell, applying a word line voltage to a word line connected to the memory cell, in order to inject hot electrons on a junction between the substrate and the first P-type doped region of the memory cell into a silicon nitride layer of the memory cell using band-to-band tunneling injection, and applying a substrate voltage to the substrates of the plurality of memory cells.
摘要翻译：一种用于写入存储器模块的方法包括提供多个存储器单元，将第一传输线电压施加到存储器单元的列的第一传输线，将存储单元之间的存储单元的P型通道导通到写入存储单元的列的第一传输线，关闭存储单元和存储单元的列的第二传输线之间的至少一个存储单元的P型通道，施加字线电压连接到连接到存储器单元的字线，以便使用带 - 带隧穿将热电子注入存储器单元的第一P型掺杂区域中的结，成为存储单元的氮化硅层注入，并且将衬底电压施加到多个存储单元的衬底。

37. 发明授权

US06801456B1 Method for programming, erasing and reading a flash memory cell 有权
标题翻译：编程，擦除和读取闪存单元的方法
公开(公告)号：US06801456B1
公开(公告)日：2004-10-05
申请号：US10707474
申请日：2003-12-17
申请人： Ching-Hsiang Hsu , Chih-Hsun Chu , Jih-Wen Chou , Cheng-Tung Huang
发明人： Ching-Hsiang Hsu , Chih-Hsun Chu , Jih-Wen Chou , Cheng-Tung Huang
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0466
摘要： A method for programming PMOS single transistor flash memory cells through channel hot carrier induced hot electron injection mechanism is disclosed. The PMOS single transistor flash memory cell includes an ONO stack layer situated on an N-well of a semiconductor substrate, a P+ poly gate formed on the ONO stack layer, a P+ doped source region disposed in the N-well at one side of the gate, and a P+ doped drain region disposed in the N-well at the other side of the gate. The method includes the steps of: applying a word line voltage VWL on the P+ poly gate, applying a source line voltage VSL on the source, wherein the source line voltage VSL is greater than the word line voltage VWL, thereby providing adequate bias to turn on the P channel thereof. A bit line voltage that is smaller than the source line voltage VSL is applied on the P+ doped drain region, thereby driving channel hot holes to flow toward the P+ doped drain region and then inducing hot electron injection near the drain side. A well voltage VNW is applied to the N-well, wherein VNW=VSL.
摘要翻译：公开了一种通过通道热载流子诱发的热电子注入机制来编程PMOS单晶体管闪存单元的方法。 PMOS单晶体管闪存单元包括位于半导体衬底的N阱上的ONO堆叠层，形成在ONO堆叠层上的P +多晶硅栅极，设置在N + 并且在栅极的另一侧设置在N阱中的P +掺杂漏极区。该方法包括以下步骤：在P ++多栅极上施加字线电压VWL，在源极上施加源极线电压VSL，其中源极线电压VSL大于字线电压VWL，从而提供足够的偏置以打开其P通道。小于源极线电压VSL的位线电压施加在P +掺杂漏极区域上，从而驱动通道热孔流向P +掺杂漏极区域，然后在漏极附近引入热电子注入侧。将井电压VNW施加到N阱，其中VNW = VSL。

38. 发明授权

US06787419B2 Method of forming an embedded memory including forming three silicon or polysilicon layers 失效
标题翻译：形成嵌入式存储器的方法，包括形成三个硅或多晶硅层
公开(公告)号：US06787419B2
公开(公告)日：2004-09-07
申请号：US10248363
申请日：2003-01-14
申请人： Chung-Yi Chen , Jih-Wen Chou , Chih-Hsun Chu
发明人： Chung-Yi Chen , Jih-Wen Chou , Chih-Hsun Chu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/32139 , H01L27/105 , H01L27/11573
摘要： A wafer has a substrate defined with a first region and a second region. An ONO layer, a first silicon layer, and a silicon nitride layer are formed on the substrate in sequence. Then the ONO layer, the first silicon layer, and the silicon nitride layer disposed on the second region are removed. At least one gate oxide layer is formed on the second region and a second silicon layer is deposited on the wafer. After that, a photo-etching process is performed to remove the second silicon layer and the silicon nitride layer on the first region. At least a third silicon layer is formed on the wafer. Photo-etching processes and a plurality of ion implantation processes are then performed to form a gate, a drain, and a source of each MOS transistor on the substrate.
摘要翻译：晶片具有限定有第一区域和第二区域的基板。依次在基板上形成ONO层，第一硅层和氮化硅层。然后去除设置在第二区域上的ONO层，第一硅层和氮化硅层。在第二区域上形成至少一个栅极氧化物层，并且在晶片上沉积第二硅层。之后，进行光蚀刻处理以去除第一区域上的第二硅层和氮化硅层。在晶片上形成至少第三硅层。然后执行光蚀刻工艺和多个离子注入工艺以在衬底上形成每个MOS晶体管的栅极，漏极和源极。

39. 发明授权

US06365475B1 Method of forming a MOS transistor 有权
标题翻译：形成MOS晶体管的方法
公开(公告)号：US06365475B1
公开(公告)日：2002-04-02
申请号：US09534537
申请日：2000-03-27
申请人： Yao-Chin Cheng , Chung-Chiang Lin , Jih-Wen Chou
发明人： Yao-Chin Cheng , Chung-Chiang Lin , Jih-Wen Chou
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/105 , H01L29/1083
摘要： The present invention provides a method of forming a Metal Oxide Semiconductor (MOS) transistor on a substrate of a semiconductor wafer. A gate of the MOS transistor is formed on the substrate. A source and a drain of the MOS transistor are then formed in the substrate. An ion implantation process is performed to form a first doped region, a second doped region and a third doped region. The first doped region is positioned under the gate and overlaps with the channel of the MOS transistor. The second doped region is positioned in a predetermined portion of the substrate under the source. The third doped region is positioned in a predetermined portion of the substrate under the drain. The first doped region, the second doped region, the third doped region, the source, and the drain are all of the same type of semiconductor.
摘要翻译：本发明提供了在半导体晶片的基板上形成金属氧化物半导体（MOS）晶体管的方法。 MOS晶体管的栅极形成在衬底上。然后在衬底中形成MOS晶体管的源极和漏极。执行离子注入工艺以形成第一掺杂区域，第二掺杂区域和第三掺杂区域。第一掺杂区位于栅极下方并与MOS晶体管的沟道重叠。第二掺杂区域位于源极下方的衬底的预定部分中。第三掺杂区位于衬底下方的漏极的预定部分。第一掺杂区域，第二掺杂区域，第三掺杂区域，源极和漏极都是相同类型的半导体。

40. 发明授权

US06297082B1 Method of fabricating a MOS transistor with local channel ion implantation regions 失效
标题翻译：用本地沟道离子注入区制造MOS晶体管的方法
公开(公告)号：US06297082B1
公开(公告)日：2001-10-02
申请号：US09383033
申请日：1999-08-25
申请人： Tony Lin , Alice Chao , Jih-Wen Chou
发明人： Tony Lin , Alice Chao , Jih-Wen Chou
IPC分类号： H01L218238
CPC分类号： H01L29/66537 , H01L21/823807 , H01L29/7833
摘要： A fabrication method for a metal oxide semiconductor (MOS) transistor involves forming gate oxide layers of different thicknesses on a core region and a input/output (I/O) region. After forming wells in the substrate, two implantation regions for providing a threshold voltage (VT) adjustment and an anti-punch through layer are formed respectively in a P-well and a N-well of the core region as well as a P-well and a N-well of the I/O region. The method involves forming a pattern mask on the gate oxide layer, wherein the pattern mask has an opening, which may be a channel that corresponds to the P-well of the core region. With the pattern mask serving as an ion implantation mask, two implantation regions for providing the VT adjustment and the anti-punch through layer are formed in the P-well of the core region. After the pattern mask is removed, the steps described above are repeated in order to form implantation regions in other regions, but the sequence of the steps can be swapped around at will. The subsequent process for the MOS transistor is then performed.
摘要翻译：金属氧化物半导体（MOS）晶体管的制造方法涉及在核心区域和输入/输出（I / O）区域上形成不同厚度的栅极氧化物层。在衬底中形成阱之后，分别在芯区的P阱和N阱以及P阱中形成用于提供阈值电压（VT）调整和抗穿通层的两个注入区域和I / O区域的N阱。该方法包括在栅极氧化物层上形成图案掩模，其中图案掩模具有开口，该开口可以是对应于核心区域的P阱的沟道。利用图案掩模作为离子注入掩模，在核心区域的P阱中形成用于提供VT调整和抗穿透层的两个注入区域。在去除图案掩模之后，重复上述步骤以在其它区域中形成植入区域，但是步骤的顺序可以随意地交换。然后执行MOS晶体管的后续处理。

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