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31. 发明申请

US20060033151A1 Flash memory having memory section and peripheral circuit section and manufacturing the same 失效
公开(公告)号：US20060033151A1
公开(公告)日：2006-02-16
申请号：US11259142
申请日：2005-10-27
申请人： Riichiro Shirota , Kikuko Sugimae , Masayuki Ichige , Atsuhiro Sato , Hiroaki Hazama
发明人： Riichiro Shirota , Kikuko Sugimae , Masayuki Ichige , Atsuhiro Sato , Hiroaki Hazama
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11536
摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.

32. 发明授权

US06977409B2 Flash memory having memory section and peripheral circuit section 失效
标题翻译：具有存储器部分和外围电路部分的闪存
公开(公告)号：US06977409B2
公开(公告)日：2005-12-20
申请号：US10685599
申请日：2003-10-16
申请人： Riichiro Shirota , Kikuko Sugimae , Masayuki Ichige , Atsuhiro Sato , Hiroaki Hazama
发明人： Riichiro Shirota , Kikuko Sugimae , Masayuki Ichige , Atsuhiro Sato , Hiroaki Hazama
IPC分类号： H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11536
摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.
摘要翻译：半导体存储器件包括半导体衬底，形成在半导体衬底中并包括用于隔离元件区的厚元件隔离绝缘膜的元件隔离区，设置在半导体衬底中的元件区域上的自对准的第一栅电极在元件隔离区域中，设置在第一栅电极上的绝缘膜的第二栅极电极和形成在元件隔离区域上的电阻元件，电阻元件和第二栅电极由相同的导电膜形成。

33. 发明申请

US20050104120A1 Non-volatile semiconductor memory device with multi-layer gate structure 失效
公开(公告)号：US20050104120A1
公开(公告)日：2005-05-19
申请号：US11020314
申请日：2004-12-27
申请人： Masayuki Ichige , Yuji Takeuchi , Michiharu Matsui , Atsuhiro Sato , Kikuko Sugimae , Riichiro Shirota
发明人： Masayuki Ichige , Yuji Takeuchi , Michiharu Matsui , Atsuhiro Sato , Kikuko Sugimae , Riichiro Shirota
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/15 , H01L21/82
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.

34. 发明申请

US20050094431A1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20050094431A1
公开(公告)日：2005-05-05
申请号：US10948295
申请日：2004-09-24
申请人： Atsuhiro Sato , Riichiro Shirota , Kikuko Sugimae , Koji Sakui
发明人： Atsuhiro Sato , Riichiro Shirota , Kikuko Sugimae , Koji Sakui
IPC分类号： G11C16/06 , G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/00
CPC分类号： G11C16/06 , G11C11/005 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , H01L27/11521 , H01L27/11546
摘要： A nonvolatile semiconductor memory includes: a memory sub array including a memory cell unit configured with a memory cell transistor and a select transistor connected in series; a control gate line driver including a control gate line driver transistor connected to a control gate line of the memory cell transistor; and a select transistor gate line driver including a select gate line driver transistor connected to a select gate line of the select transistor. A thickness of a gate insulator of the control gate line driver transistor is thicker than that of the select gate line driver transistor.
摘要翻译：非易失性半导体存储器包括：存储器子阵列，包括配置有存储单元晶体管的存储单元单元和串联连接的选择晶体管; 控制栅极线驱动器，包括连接到存储单元晶体管的控制栅极线的控制栅极线驱动晶体管; 以及选择晶体管栅极线驱动器，其包括连接到选择晶体管的选择栅极线的选择栅极线驱动晶体管。控制栅极线驱动晶体管的栅极绝缘体的厚度比选择栅线驱动晶体管的厚度厚。

35. 发明申请

US20050067652A1 Nonvolatile semiconductor memory and a fabrication method thereof 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20050067652A1
公开(公告)日：2005-03-31
申请号：US10868806
申请日：2004-06-17
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction making a striped pattern along the column direction. The control gates are continuously deployed along the row direction, and the inter-gate insulating films are in series along the column direction and separated from each other at a constant pitch along the row direction.
摘要翻译：非易失性半导体存储器包括分别具有浮置栅极，控制栅极和栅极间绝缘膜的多个存储单元晶体管，其分别布置在相应的浮置栅极和相应的控制栅极之间，并沿着列方向展开; 以及沿着行方向以恒定间距部署的器件隔离区域，沿着列方向形成条纹图案。控制栅极沿着行方向连续展开，并且栅极间绝缘膜沿列方向串联并沿行方向以恒定的间距彼此分离。

36. 发明授权

US08541829B2 Nonvolatile semiconductor memory and fabrication method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法相同
公开(公告)号：US08541829B2
公开(公告)日：2013-09-24
申请号：US13235948
申请日：2011-09-19
申请人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
发明人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
IPC分类号： H01L29/76 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor.
摘要翻译：非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧穿绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层以及第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层以及第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在每个存储单元晶体管，低压晶体管和高压晶体管的源极和漏极区域上的衬垫绝缘膜。

37. 发明授权

US08159880B2 NAND flash memory 失效
标题翻译： NAND闪存
公开(公告)号：US08159880B2
公开(公告)日：2012-04-17
申请号：US13164486
申请日：2011-06-20
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： G11C16/00
CPC分类号： G11C11/5628 , G11C16/0483
摘要： In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the memory cell transistors and which is to be cut off, a second voltage which is higher than the first voltage and which causes a plurality of third memory cell transistors remaining unselected in the memory cell transistors to conduct is applied to control gates of the third memory cell transistors, and thereafter a threshold voltage of the first memory cell transistor is changed to a threshold voltage higher than the first threshold voltage corresponding to the erase state by applying a third voltage which is higher than the second voltage to a control gate of the first memory cell transistor.
摘要翻译：在第一和第二选择栅极晶体管被截止并且第一电压被施加到第二存储单元晶体管的控制栅极的状态下，第二存储单元晶体管连接到从存储器中选择的第一存储单元晶体管的源极线侧单元晶体管并且要被切断，高于第一电压的第二电压并且使得在存储单元晶体管导通时保持未选择的多个第三存储单元晶体管被施加到第三存储单元晶体管的控制栅极之后，通过向第一存储单元的控制栅极施加高于第二电压的第三电压，将第一存储单元晶体管的阈值电压改变为高于与擦除状态相对应的第一阈值电压的阈值电压晶体管。

38. 发明授权

US08139407B2 Nonvolatile semiconductor memory device including NAND-type flash memory and the like 有权
标题翻译：包括NAND型闪存等的非易失性半导体存储器件
公开(公告)号：US08139407B2
公开(公告)日：2012-03-20
申请号：US12955621
申请日：2010-11-29
申请人： Atsuhiro Sato , Keiji Shuto , Fumitaka Arai
发明人： Atsuhiro Sato , Keiji Shuto , Fumitaka Arai
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3418 , G11C11/5642 , G11C16/0483 , G11C2211/5642
摘要： A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
摘要翻译：非易失性半导体存储器件设置有存储单元阵列，判断电位校正电路和读出电路。在存储单元阵列中，以矩阵形式布置多个存储单元，并且阵列包括作为读出对象的第一存储单元和与第一存储单元相邻设置的第二存储单元。判定电位校正电路根据第二存储单元的阈值校正判定电位。读出电路通过使用校正的判断电位读出作为读出对象的第一存储单元。

39. 发明授权

US08133782B2 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08133782B2
公开(公告)日：2012-03-13
申请号：US13028730
申请日：2011-02-16
申请人： Hiroshi Akahori , Wakako Takeuchi , Atsuhiro Sato
发明人： Hiroshi Akahori , Wakako Takeuchi , Atsuhiro Sato
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42336
摘要： A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.
摘要翻译：存储器件包括：半导体衬底，以行和列形成在衬底上方的存储元件，位线和字线与各个列和行中的存储元件选择性地连接，每个存储元件包括形成在衬底上的第一栅极绝缘体，形成在第一栅极绝缘体上的电荷累积层，形成在电荷累积层上的第二栅极绝缘体和形成在第二栅极绝缘体上的控制电极，其中比率r / d不小于0.5，其中r：a 上角部的曲率半径或电荷蓄积层的表面粗糙度，d：沿着与位线垂直的方向的截面中的第二栅极绝缘体的等效氧化物厚度。

40. 发明授权

US08088661B2 Nonvolatile semiconductor memory with resistance elements and method of manufacturing the same 失效
标题翻译：具有电阻元件的非易失性半导体存储器及其制造方法
公开(公告)号：US08088661B2
公开(公告)日：2012-01-03
申请号：US12652548
申请日：2010-01-05
申请人： Fumitaka Arai , Atsuhiro Sato
发明人： Fumitaka Arai , Atsuhiro Sato
IPC分类号： H01L29/72
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11539 , H01L29/78
摘要： A nonvolatile semiconductor memory of an aspect of the present invention comprises a memory cell transistor and a resistance element arranged on a semiconductor substrate. The memory cell transistor includes a floating gate electrode constituted of a first conductive material arranged on a gate insulating film on a surface of the semiconductor substrate, an inter-gate insulating film arranged on the floating gate electrode, a control gate electrode arranged on the inter-gate insulating film, and a source/drain diffusion layer provided in the semiconductor substrate. The resistance element includes an element isolation insulating layer arranged in the semiconductor substrate and including a depression, and a resistor constituted of a second conductive material filling up the depression. An impurity concentration of the second conductive material is lower than that of the first conductive material.
摘要翻译：本发明的一个方面的非易失性半导体存储器包括存储单元晶体管和布置在半导体衬底上的电阻元件。存储单元晶体管包括由在半导体衬底的表面上配置在栅极绝缘膜上的第一导电材料构成的浮置栅极电极，布置在浮置栅电极上的栅极间绝缘膜，栅极绝缘膜和设置在半导体衬底中的源极/漏极扩散层。电阻元件包括布置在半导体衬底中并包括凹陷的元件隔离绝缘层和由填充凹陷的第二导电材料构成的电阻器。第二导电材料的杂质浓度低于第一导电材料的杂质浓度。

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