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1. 发明授权

US07649221B2 Nonvolatile semiconductor memory and a fabrication method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07649221B2
公开(公告)日：2010-01-19
申请号：US11951026
申请日：2007-12-05
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L29/72
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.
摘要翻译：非易失性半导体存储器包括：多个存储单元晶体管，其配置有分别布置在第一浮置栅极和第一控制栅极之间的第一浮动栅极，第一控制栅极和第一栅极间绝缘膜，并且它们对准沿着位线方向; 器件隔离区沿着字线方向以恒定的间距设置，沿着位线方向形成条纹图案; 并且选择栅极晶体管，其设置在存储单元晶体管的对准的每一端，每个配置有第二浮置栅极，第二控制栅极，设置在第二浮置栅极和第二控制栅极之间的第二栅极间绝缘膜，以及电连接到第二浮动栅极和第二控制栅极的侧壁栅极。

2. 发明授权

US07505312B2 Nonvolatile semiconductor memory device capable of controlling proximity effect due to coupling between adjacent charge storage layers 有权
标题翻译：能够通过相邻电荷存储层之间的耦合来控制邻近效应的非易失性半导体存储器件
公开(公告)号：US07505312B2
公开(公告)日：2009-03-17
申请号：US11447963
申请日：2006-06-07
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
IPC分类号： G11C16/10
CPC分类号： G11C16/3418 , G11C16/3427
摘要： There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.
摘要翻译：公开了一种包括具有多个块的存储单元阵列的半导体集成电路器件，布置在存储单元阵列中并具有电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体存储单元，布置在与第一非易失性半导体存储单元相邻的存储单元阵列中，并具有电荷存储层。在相对于第一非易失性半导体存储单元执行常规数据写入之后，相对于第二非易失性半导体存储单元执行正常数据写入。在相对于第二非易失性半导体存储单元执行常规数据写入之后，相对于第一非易失性半导体存储单元执行附加数据写入。

3. 发明授权

US07122430B2 Nonvolatile semiconductor memory and manufacturing method for the same 失效
公开(公告)号：US07122430B2
公开(公告)日：2006-10-17
申请号：US11311262
申请日：2005-12-20
申请人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
发明人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
IPC分类号： H01I21/336 , H01I21/8238
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529
摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.

4. 发明申请

US20050067652A1 Nonvolatile semiconductor memory and a fabrication method thereof 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20050067652A1
公开(公告)日：2005-03-31
申请号：US10868806
申请日：2004-06-17
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction making a striped pattern along the column direction. The control gates are continuously deployed along the row direction, and the inter-gate insulating films are in series along the column direction and separated from each other at a constant pitch along the row direction.
摘要翻译：非易失性半导体存储器包括分别具有浮置栅极，控制栅极和栅极间绝缘膜的多个存储单元晶体管，其分别布置在相应的浮置栅极和相应的控制栅极之间，并沿着列方向展开; 以及沿着行方向以恒定间距部署的器件隔离区域，沿着列方向形成条纹图案。控制栅极沿着行方向连续展开，并且栅极间绝缘膜沿列方向串联并沿行方向以恒定的间距彼此分离。

5. 发明授权

US07393747B2 Nonvolatile semiconductor memory and a fabrication method thereof 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07393747B2
公开(公告)日：2008-07-01
申请号：US11337001
申请日：2006-01-23
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction making a striped pattern along the column direction. The control gates are continuously deployed along the row direction, and the inter-gate insulating films are in series along the column direction and separated from each other at a constant pitch along the row direction.
摘要翻译：非易失性半导体存储器包括分别具有浮置栅极，控制栅极和栅极间绝缘膜的多个存储单元晶体管，其分别布置在相应的浮置栅极和相应的控制栅极之间，并沿着列方向展开; 以及沿着行方向以恒定间距部署的器件隔离区域，沿着列方向形成条纹图案。控制栅极沿着行方向连续展开，并且栅极间绝缘膜沿列方向串联并沿行方向以恒定的间距彼此分离。

6. 发明授权

US07335938B2 Nonvolatile semiconductor memory and a fabrication method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07335938B2
公开(公告)日：2008-02-26
申请号：US10971161
申请日：2004-10-25
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L29/72
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.
摘要翻译：非易失性半导体存储器包括：多个存储单元晶体管，其配置有分别布置在第一浮置栅极和第一控制栅极之间的第一浮动栅极，第一控制栅极和第一栅极间绝缘膜，并且它们对准沿着位线方向; 器件隔离区沿着字线方向以恒定的间距设置，沿着位线方向形成条纹图案; 并且选择栅极晶体管，其设置在存储单元晶体管的对准的每一端，每个配置有第二浮置栅极，第二控制栅极，设置在第二浮置栅极和第二控制栅极之间的第二栅极间绝缘膜，以及电连接到第二浮动栅极和第二控制栅极的侧壁栅极。

7. 发明申请

US20060131638A1 Nonvolatile semiconductor memory and a fabrication method thereof 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20060131638A1
公开(公告)日：2006-06-22
申请号：US11337001
申请日：2006-01-23
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction making a striped pattern along the column direction. The control gates are continuously deployed along the row direction, and the inter-gate insulating films are in series along the column direction and separated from each other at a constant pitch along the row direction.
摘要翻译：非易失性半导体存储器包括分别具有浮置栅极，控制栅极和栅极间绝缘膜的多个存储单元晶体管，其分别布置在相应的浮置栅极和相应的控制栅极之间，并沿着列方向展开; 以及沿着行方向以恒定间距部署的器件隔离区域，沿着列方向形成条纹图案。控制栅极沿着行方向连续展开，并且栅极间绝缘膜沿列方向串联并沿行方向以恒定的间距彼此分离。

8. 发明申请

US20050199938A1 Nonvolatile semiconductor memory and a fabrication method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20050199938A1
公开(公告)日：2005-09-15
申请号：US10971161
申请日：2004-10-25
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.
摘要翻译：非易失性半导体存储器包括：多个存储单元晶体管，其配置有分别布置在第一浮置栅极和第一控制栅极之间的第一浮动栅极，第一控制栅极和第一栅极间绝缘膜，并且它们对准沿着位线方向; 器件隔离区沿着字线方向以恒定的间距设置，沿着位线方向形成条纹图案; 并且选择栅极晶体管，其设置在存储单元晶体管的对准的每一端，每个配置有第二浮置栅极，第二控制栅极，设置在第二浮置栅极和第二控制栅极之间的第二栅极间绝缘膜，以及电连接到第二浮动栅极和第二控制栅极的侧壁栅极。

9. 发明申请

US20080076245A1 NONVOLATILE SEMICONDUCTOR MEMORY AND A FABRICATION METHOD FOR THE SAME 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20080076245A1
公开(公告)日：2008-03-27
申请号：US11947396
申请日：2007-11-29
申请人： Makoto SAKUMA , Atsuhiro Sato
发明人： Makoto SAKUMA , Atsuhiro Sato
IPC分类号： H01L21/44
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.
摘要翻译：非易失性半导体存储器包括：多个存储单元晶体管，其配置有分别布置在第一浮置栅极和第一控制栅极之间的第一浮动栅极，第一控制栅极和第一栅极间绝缘膜，并且它们对准沿着位线方向; 器件隔离区沿着字线方向以恒定的间距设置，沿着位线方向形成条纹图案; 并且选择栅极晶体管，其设置在存储单元晶体管的对准的每一端，每个配置有第二浮置栅极，第二控制栅极，设置在第二浮置栅极和第二控制栅极之间的第二栅极间绝缘膜，以及电连接到第二浮动栅极和第二控制栅极的侧壁栅极。

10. 发明授权

US07019355B2 Nonvolatile semiconductor memory and a fabrication method thereof 失效
公开(公告)号：US07019355B2
公开(公告)日：2006-03-28
申请号：US10868806
申请日：2004-06-17
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction making a striped pattern along the column direction. The control gates are continuously deployed along the row direction, and the inter-gate insulating films are in series along the column direction and separated from each other at a constant pitch along the row direction.

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