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1. 发明授权

US08139407B2 Nonvolatile semiconductor memory device including NAND-type flash memory and the like 有权
标题翻译：包括NAND型闪存等的非易失性半导体存储器件
公开(公告)号：US08139407B2
公开(公告)日：2012-03-20
申请号：US12955621
申请日：2010-11-29
申请人： Atsuhiro Sato , Keiji Shuto , Fumitaka Arai
发明人： Atsuhiro Sato , Keiji Shuto , Fumitaka Arai
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3418 , G11C11/5642 , G11C16/0483 , G11C2211/5642
摘要： A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
摘要翻译：非易失性半导体存储器件设置有存储单元阵列，判断电位校正电路和读出电路。在存储单元阵列中，以矩阵形式布置多个存储单元，并且阵列包括作为读出对象的第一存储单元和与第一存储单元相邻设置的第二存储单元。判定电位校正电路根据第二存储单元的阈值校正判定电位。读出电路通过使用校正的判断电位读出作为读出对象的第一存储单元。

2. 发明授权

US07859898B2 Nonvolatile semiconductor memory device including NAND-type flash memory and the like 有权
标题翻译：包括NAND型闪存等的非易失性半导体存储器件
公开(公告)号：US07859898B2
公开(公告)日：2010-12-28
申请号：US12354946
申请日：2009-01-16
申请人： Atsuhiro Sato , Keiji Shuto , Fumitaka Arai
发明人： Atsuhiro Sato , Keiji Shuto , Fumitaka Arai
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3418 , G11C11/5642 , G11C16/0483 , G11C2211/5642
摘要： A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
摘要翻译：非易失性半导体存储器件设置有存储单元阵列，判断电位校正电路和读出电路。在存储单元阵列中，以矩阵形式布置多个存储单元，并且阵列包括作为读出对象的第一存储单元和与第一存储单元相邻设置的第二存储单元。判定电位校正电路根据第二存储单元的阈值校正判定电位。读出电路通过使用校正的判断电位读出作为读出对象的第一存储单元。

3. 发明授权

US07505312B2 Nonvolatile semiconductor memory device capable of controlling proximity effect due to coupling between adjacent charge storage layers 有权
标题翻译：能够通过相邻电荷存储层之间的耦合来控制邻近效应的非易失性半导体存储器件
公开(公告)号：US07505312B2
公开(公告)日：2009-03-17
申请号：US11447963
申请日：2006-06-07
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
IPC分类号： G11C16/10
CPC分类号： G11C16/3418 , G11C16/3427
摘要： There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.
摘要翻译：公开了一种包括具有多个块的存储单元阵列的半导体集成电路器件，布置在存储单元阵列中并具有电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体存储单元，布置在与第一非易失性半导体存储单元相邻的存储单元阵列中，并具有电荷存储层。在相对于第一非易失性半导体存储单元执行常规数据写入之后，相对于第二非易失性半导体存储单元执行正常数据写入。在相对于第二非易失性半导体存储单元执行常规数据写入之后，相对于第一非易失性半导体存储单元执行附加数据写入。

4. 发明申请

US20070177431A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20070177431A1
公开(公告)日：2007-08-02
申请号：US11447963
申请日：2006-06-07
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.
摘要翻译：公开了一种包括具有多个块的存储单元阵列的半导体集成电路器件，布置在存储单元阵列中并具有电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体存储单元，布置在与第一非易失性半导体存储单元相邻的存储单元阵列中，并具有电荷存储层。在相对于第一非易失性半导体存储单元执行常规数据写入之后，相对于第二非易失性半导体存储单元执行正常数据写入。在相对于第二非易失性半导体存储单元执行常规数据写入之后，相对于第一非易失性半导体存储单元执行附加数据写入。

5. 发明申请

US20070159881A1 Nonvolatile semiconductor memory device including nand-type flash memory and the like 审中-公开
标题翻译：包括n型闪速存储器等的非易失性半导体存储器件
公开(公告)号：US20070159881A1
公开(公告)日：2007-07-12
申请号：US11474340
申请日：2006-06-26
申请人： Atsuhiro Sato , Keiji Shuto , Fumitaka Arai
发明人： Atsuhiro Sato , Keiji Shuto , Fumitaka Arai
IPC分类号： G11C16/04 , G11C11/34 , G11C16/06
CPC分类号： G11C16/3418 , G11C11/5642 , G11C16/0483 , G11C2211/5642
摘要： A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
摘要翻译：非易失性半导体存储器件设置有存储单元阵列，判断电位校正电路和读出电路。在存储单元阵列中，以矩阵形式布置多个存储单元，并且阵列包括作为读出对象的第一存储单元和与第一存储单元相邻设置的第二存储单元。判定电位校正电路根据第二存储单元的阈值校正判定电位。读出电路通过使用校正的判断电位读出作为读出对象的第一存储单元。

6. 发明授权

US08377814B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08377814B2
公开(公告)日：2013-02-19
申请号：US13164931
申请日：2011-06-21
申请人： Atsuhiro Sato , Hiroyuki Nitta , Fumitaka Arai
发明人： Atsuhiro Sato , Hiroyuki Nitta , Fumitaka Arai
IPC分类号： H01L21/28
CPC分类号： H01L27/11524 , H01L21/76816 , H01L27/11521
摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.
摘要翻译：半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

7. 发明授权

US08120092B2 Semiconductor memory device and manufacturing method therefor 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08120092B2
公开(公告)日：2012-02-21
申请号：US12565181
申请日：2009-09-23
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11529
摘要： First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode.
摘要翻译：存储单元晶体管的第一栅电极在半导体衬底上彼此串联形成。第一选择晶体管的第二栅电极与第一电极的一端相邻地形成。第二选择晶体管的第三栅电极与第二电极相邻地形成。在基板上形成周边晶体管的第四栅电极。第一，第二和第三侧壁膜分别形成在第二，第三和第四栅电极的侧表面上。第三侧壁膜的膜厚大于第一和第二侧壁膜的膜厚。第一电极和第二电极之间的空间大于第一电极之间的空间，并且第二电极和第三电极之间的间隔大于第一电极和第二电极之间的间隔。

8. 发明授权

US07122430B2 Nonvolatile semiconductor memory and manufacturing method for the same 失效
公开(公告)号：US07122430B2
公开(公告)日：2006-10-17
申请号：US11311262
申请日：2005-12-20
申请人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
发明人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
IPC分类号： H01I21/336 , H01I21/8238
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529
摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.

9. 发明授权

US08314455B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08314455B2
公开(公告)日：2012-11-20
申请号：US13156727
申请日：2011-06-09
申请人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
发明人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译：非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。

10. 发明申请

US20120094461A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120094461A1
公开(公告)日：2012-04-19
申请号：US13332462
申请日：2011-12-21
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L21/8234
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11529
摘要： First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode.
摘要翻译：存储单元晶体管的第一栅电极在半导体衬底上彼此串联形成。第一选择晶体管的第二栅电极与第一电极的一端相邻地形成。第二选择晶体管的第三栅电极与第二电极相邻地形成。在基板上形成周边晶体管的第四栅电极。第一，第二和第三侧壁膜分别形成在第二，第三和第四栅电极的侧表面上。第三侧壁膜的膜厚大于第一和第二侧壁膜的膜厚。第一电极和第二电极之间的空间大于第一电极之间的空间，并且第二电极和第三电极之间的间隔大于第一电极和第二电极之间的间隔。

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