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31. 发明授权

US08363736B2 Test circuit for serial link receiver 失效
标题翻译：串行链路接收机测试电路
公开(公告)号：US08363736B2
公开(公告)日：2013-01-29
申请号：US13044604
申请日：2011-03-10
申请人： Hayden C. Cranford , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
发明人： Hayden C. Cranford , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
IPC分类号： H04L25/00 , H04B17/00
CPC分类号： G01R31/31715
摘要： A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.
摘要翻译：用于串行链路接收机的测试电路包括耦合到串行链路接收机的第一输入端的第一电流源和耦合到串行链路接收机的第二输入端的第二电流源。第一电流源与第二电流源对称地匹配。第一电流源的第一开关被接通以允许其电荷保持机构被充电。第一电流源的第二开关导通，以允许保留的保留电荷在第一输入上被断言。电荷打开第一个电流源的控制开关，电荷在第一个输入端被断言。接通第一电流源的电荷排放机构，之后允许电荷在电荷被断言之后以受控的方式排出。

32. 发明授权

US07486127B2 Transistor switch with integral body connection to prevent latchup 失效
标题翻译：晶体管开关具有整体连接，以防止闭锁
公开(公告)号：US07486127B2
公开(公告)日：2009-02-03
申请号：US11835298
申请日：2007-08-07
申请人： Hayden C. Cranford , Stacy J. Garvin , Todd M. Rasmus
发明人： Hayden C. Cranford , Stacy J. Garvin , Todd M. Rasmus
IPC分类号： H03K3/01
CPC分类号： H03K17/161 , H03K2217/0018
摘要： A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) transistor so that an integral body connection is provided for the switching transistor, which connects the body of the switching transistor to a node between the pull-up resistor and source terminal of the LVT transistor. The LVT transistor is connected with its gate and drain terminal connected to the output terminal of the switching transistor. The resistor is connected at its other end to the power supply side terminal of the switching transistor. The addition of these components in the particular configuration allows the body connection of the switching transistor to be automatically switched to the highest potential diffusion node.
摘要翻译：一种具有基于晶体管的开关拓扑的电路器件，其基本上消除了器件闭锁的可能性。串联的低电压阈值（LVT）N沟道晶体管和上拉电阻跨越开关（P沟道）晶体管耦合，以便为开关晶体管提供一体的主体连接，开关晶体管连接开关晶体管连接到LVT晶体管的上拉电阻和源极端子之间的一个节点。 LVT晶体管的栅极和漏极端子连接到开关晶体管的输出端子。电阻器的另一端连接到开关晶体管的电源侧端子。在特定配置中添加这些组件允许开关晶体管的主体连接自动切换到最高电位扩散节点。

33. 发明申请

US20080218229A1 ADJUSTMENT OF PLL BANDWIDTH FOR JITTER CONTROL USING FEEDBACK CIRCUITRY 审中-公开
标题翻译：使用反馈电路调整抖动控制的PLL带宽
公开(公告)号：US20080218229A1
公开(公告)日：2008-09-11
申请号：US12100485
申请日：2008-04-10
申请人： Hayden C. Cranford , Ram Kelkar , Anjali R. Malladi , Martin L. Schmatz , Nina A. Shah
发明人： Hayden C. Cranford , Ram Kelkar , Anjali R. Malladi , Martin L. Schmatz , Nina A. Shah
IPC分类号： H03L7/06
CPC分类号： H03L7/02
摘要： Jitter method and control circuit for a circuit block in a transceiver system having a phase lock loop circuit which includes an oscillator, a charge pump connected to the oscillator to add or subtract charge to or from said oscillator, and a low pass filter connected to said charge pump are provided. Circuitry is connected to the output of the oscillator and the input of the charge pump to control the amount of charge added to or subtracted from the charge pump to control the bandwidth output by the oscillator and thereby reduce jitter in the phase lock circuit.
摘要翻译：具有锁相环电路的收发器系统中的电路块的抖动方法和控制电路，该锁相环电路包括振荡器，连接到所述振荡器的电荷泵以向所述振荡器加上或从所述振荡器加减电荷，以及连接到所述振荡器的低通滤波器提供电荷泵。电路连接到振荡器的输出端和电荷泵的输入端，以控制从电荷泵加到或减去的电荷量，以控制振荡器的带宽输出，从而减少锁相电路中的抖动。

34. 发明申请

US20080177489A1 SYSTEM AND CIRCUIT FOR CONSTRUCTING A SYNCHRONOUS SIGNAL DIAGRAM FROM ASYNCHRONOUSLY SAMPLED DATA 有权
标题翻译：用于从非同步采样数据构建同步信号图的系统和电路
公开(公告)号：US20080177489A1
公开(公告)日：2008-07-24
申请号：US12055317
申请日：2008-03-26
申请人： Hayden C. Cranford , Fadi H. Gebara , Jeremy D. Schaub
发明人： Hayden C. Cranford , Fadi H. Gebara , Jeremy D. Schaub
IPC分类号： G01R13/00 , G06F17/18 , G01R29/26
CPC分类号： H04L1/205 , G01R31/31709
摘要： A system and circuit for constructing a synchronous signal diagram from asynchronous sampled data provides a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronously sampled (or alternatively a clock signal is latched). The data signal or a second signal is compared to a settable threshold voltage and sampled. The edge and comparison data are folded according to a swept timebase to find a minimum jitter period. The crossing of the signal diagram edges is determined from a peak of a histogram of the folded edge data. A histogram of ratios of the sample values versus displacement from the position of the crossing location is generated for each threshold voltage. The technique is repeated over a range of settable threshold voltages. Then, the ratio counts are differentiated across the histograms with respect to threshold voltage, from which a signal diagram is populated.
摘要翻译：用于从异步采样数据构建同步信号图的系统和电路为提供信号图提供了低成本和生产可集成技术。数据信号被边缘检测和异步采样（或者时钟信号被锁存）。将数据信号或第二信号与可设置的阈值电压进行比较并采样。边缘和比较数据根据扫描时基折叠以找到最小抖动周期。信号图边缘的交叉由折叠边缘数据的直方图的峰值确定。对于每个阈值电压产生样本值与交叉位置位置之间的位移比率的直方图。该技术在可设置的阈值电压范围内重复。然后，相对于阈值电压，在直方图之间区分比率计数，从中填充信号图。

35. 发明申请

US20080137790A1 Systems and Arrangements for Clock and Data Recovery in Communications 有权
标题翻译：通信中时钟和数据恢复的系统和布置
公开(公告)号：US20080137790A1
公开(公告)日：2008-06-12
申请号：US11608962
申请日：2006-12-11
申请人： Hayden C. Cranford , Daniel J. Friedman , Mounir Meghelli , Thomas H. Toifl
发明人： Hayden C. Cranford , Daniel J. Friedman , Mounir Meghelli , Thomas H. Toifl
IPC分类号： H04L7/00
CPC分类号： H04L7/0004 , H04L7/0334
摘要： A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the DRR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.
摘要翻译：公开了一种双模式时钟和数据恢复（CDR）系统。快速锁定，过采样CDR采集模块可以开始该过程，以在启动数据采集条件下快速创建数据采集时钟信号。当从输入数据流中提取至少一些数据时，DRR系统可以指示这种稳定性，并切换到接受来自低功率CDR维护模块的控制。低功率CDR维护模块可以微调并保持数据采集信号的定时。如果CDR维护模块控制下的数据锁定质量下降到足够的程度，高功率CDR采集模块可以重新启用并重新从低功率模块重新进行控制，直到锁定质量再次足够要使用的低功耗模块。

36. 发明申请

US20080120838A1 Impedance Calibration for Source Series Terminated Serial Link Transmitter 失效
标题翻译：源串联终端串行链路发射机的阻抗校准
公开(公告)号：US20080120838A1
公开(公告)日：2008-05-29
申请号：US12028439
申请日：2008-02-08
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford , Vernon R. Norman
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford , Vernon R. Norman
IPC分类号： H01R43/00
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.
摘要翻译：将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。

37. 发明申请

US20080111633A1 Systems and Arrangements for Controlling Phase Locked Loop 审中-公开
标题翻译：控制锁相环的系统和布置
公开(公告)号：US20080111633A1
公开(公告)日：2008-05-15
申请号：US11558127
申请日：2006-11-09
申请人： Hayden C. Cranford , Marcel A. Kossel , Thomas H. Toifl
发明人： Hayden C. Cranford , Marcel A. Kossel , Thomas H. Toifl
IPC分类号： H03L7/089
CPC分类号： H03L7/107 , H03L7/0898 , H03L7/095 , H03L7/1072 , H03L7/23
摘要： A multi-Gigahertz, low jitter phase locked loop (PLL) with adjustable gain is disclosed. In one embodiment, properties of a fVCO signal of a PLL can be acquired. Properties can include the occurrences of different types of jitter on the fVCO signal and the lock status of the PLL. A gain control module can control at least a portion of the PLL based on an analysis of the acquired properties. For example, when the loop is locked or when there is loop filter leakage, the gain of a charge pump in the PLL can be reduced. When a charge pump mismatch is detected based on the acquired properties, additional control signals can be provided to the charge pump to correct the mismatch.
摘要翻译：公开了一种具有可调增益的多吉赫兹低抖动锁相环（PLL）。在一个实施例中，可以获取PLL的f VCO信号的特性。属性可以包括在VCO上的不同类型的抖动的出现以及PLL的锁定状态。增益控制模块可以基于所获取的属性的分析来控制PLL的至少一部分。例如，当环路被锁定或者当存在环路滤波器泄漏时，可以减小PLL中的电荷泵的增益。当基于获取的特性检测到电荷泵不匹配时，可以向电荷泵提供额外的控制信号以校正不匹配。

38. 发明申请

US20080007345A1 ADJUSTMENT OF PLL BANDWIDTH FOR JITTER CONTROL USING FEEDBACK CIRCUITRY 失效
公开(公告)号：US20080007345A1
公开(公告)日：2008-01-10
申请号：US11425752
申请日：2006-06-22
申请人： Hayden C. Cranford , Ram Kelkar , Anjali R Malladi , Martin L. Schmatz , Nina A. Shah
发明人： Hayden C. Cranford , Ram Kelkar , Anjali R Malladi , Martin L. Schmatz , Nina A. Shah
IPC分类号： H03L7/00
CPC分类号： H03L7/02
摘要： Jitter method and control circuit for a circuit block in a transceiver system having a phase lock loop circuit which includes an oscillator, a charge pump connected to the oscillator to add or subtract charge to or from said oscillator, and a low pass filter connected to said charge pump are provided. Circuitry is connected to the output of the oscillator and the input of the charge pump to control the amount of charge added to or subtracted from the charge pump to control the bandwidth output by the oscillator and thereby reduce jitter in the phase lock circuit.

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