专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06968413B2 Method and system for configuring terminators in a serial communication system 有权
标题翻译：用于在串行通信系统中配置终端器的方法和系统
公开(公告)号：US06968413B2
公开(公告)日：2005-11-22
申请号：US10266132
申请日：2002-10-07
申请人： Hayden C. Cranford, Jr. , Westerfield J. Ficken , Paul A. Owczarski
发明人： Hayden C. Cranford, Jr. , Westerfield J. Ficken , Paul A. Owczarski
IPC分类号： G06F13/00 , H04L25/02
CPC分类号： H04L25/0278
摘要： A system and method is disclosed that efficiently provides standard termination blocks in an approved cell library that are flexible and customizable. A serial communications system includes a transmitter for sending a serial data signal at an output of the transmitter; a transmitter terminator, coupled to the output and responsive to a first configuration signal, to variably terminate a first selected property of the output; a receiver for processing the serial data signal at an input of the receiver, the input of the receiver coupled to the output of the transmitter; and a receiver terminator, coupled to the input of the receiver and responsive to a second configuration signal to variably terminate a second selected properly of the input. The method for operating a serial communications system includes the steps of: (a) providing a plurality of unidirectional serial links, each of the links between a transmitter and a receiver, an output of each transmitter coupled to an input of a corresponding receiver by a medium type with each output having a transmitter terminator and each input having a receiver terminator; (b) terminating variably a selected property of the output of each transmitter to match the medium type coupling the output to the input of the corresponding receiver by use of a transmitter termination configuration signal asserted to the transmitter; and (c) terminating variably a selected property of the input of each receiver to match the medium type coupling the input to the output of the corresponding transmitter by use of a receiver termination configuration signal asserted to the receiver.
摘要翻译：公开了一种系统和方法，其有效地提供了可被灵活和可定制的批准的小区库中的标准终端块。串行通信系统包括用于在发射机的输出端发送串行数据信号的发射机; 发射器终端器，耦合到所述输出并且响应于第一配置信号可变地终止所述输出的第一选定属性; 用于在接收机的输入端处理串行数据信号的接收机，耦合到发射机的输出的接收机的输入; 以及接收器终端器，其耦合到所述接收器的输入并且响应于第二配置信号可变地终止所选输入的第二选择。用于操作串行通信系统的方法包括以下步骤：（a）提供多个单向串行链路，发射机和接收机之间的每个链路，每个发射机的输出端通过一个中间型，每个输出具有发射器终端器，每个输入具有接收器终端器; （b）可变地终止每个发射机的输出的选定属性，以使得通过使用被确定给发射机的发射机终端配置信号将输出耦合到相应接收机的输入的媒体类型; 以及（c）可变地终止每个接收机的输入的选定属性以将通过使用被确认给接收机的接收机终端配置信号将输入耦合到相应发射机的输出的媒体类型。

2. 发明授权

US07332932B2 Serial link receiver with wide input voltage range and tolerance to high power voltage supply 有权
标题翻译：具有宽输入电压范围的串行链路接收器和高电源电压容限
公开(公告)号：US07332932B2
公开(公告)日：2008-02-19
申请号：US11417626
申请日：2006-05-04
申请人： Hayden C. Cranford , Westerfield J. Ficken , David A. Freitas , Joseph M. Stevens
发明人： Hayden C. Cranford , Westerfield J. Ficken , David A. Freitas , Joseph M. Stevens
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0175
CPC分类号： H03F3/45475 , H03F1/52 , H03F3/45973 , H03F2203/45078 , H03F2203/45431 , H03F2203/45541 , H03F2203/45561 , H03F2203/45588
摘要： A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamplifier and a common mode feedback loop, which monitors shifts in the common mode voltage and adjusts the inputs provided to the preamplifier. The circuit device maintains a flat bandwidth to accommodate all signaling rates.
摘要翻译：一种用于设计串行链路接收机的电路装置和方法，其适应宽的输入电压范围并且提供对高终端电压的容限。接收机设计有一对连接在输入和前置放大器之间的RC网络和一个共模反馈环路，它监控共模电压的变化并调整提供给前置放大器的输入。电路设备保持平坦的带宽以适应所有信令速率。

3. 发明申请

US20110156663A1 TEST CIRCUIT FOR SERIAL LINK RECEIVER 失效
标题翻译：串行接收器测试电路
公开(公告)号：US20110156663A1
公开(公告)日：2011-06-30
申请号：US13044604
申请日：2011-03-10
申请人： Hayden C. Cranford , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
发明人： Hayden C. Cranford , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
IPC分类号： H02J7/00
CPC分类号： G01R31/31715
摘要： A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.
摘要翻译：用于串行链路接收机的测试电路包括耦合到串行链路接收机的第一输入端的第一电流源和耦合到串行链路接收机的第二输入端的第二电流源。第一电流源与第二电流源对称地匹配。第一电流源的第一开关被接通以允许其电荷保持机构被充电。第一电流源的第二开关导通，以允许保留的保留电荷在第一输入上被断言。电荷打开第一个电流源的控制开关，电荷在第一个输入端被断言。接通第一电流源的电荷排放机构，之后允许电荷在电荷被断言之后以受控的方式排出。

4. 发明授权

US08363736B2 Test circuit for serial link receiver 失效
标题翻译：串行链路接收机测试电路
公开(公告)号：US08363736B2
公开(公告)日：2013-01-29
申请号：US13044604
申请日：2011-03-10
申请人： Hayden C. Cranford , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
发明人： Hayden C. Cranford , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
IPC分类号： H04L25/00 , H04B17/00
CPC分类号： G01R31/31715
摘要： A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.
摘要翻译：用于串行链路接收机的测试电路包括耦合到串行链路接收机的第一输入端的第一电流源和耦合到串行链路接收机的第二输入端的第二电流源。第一电流源与第二电流源对称地匹配。第一电流源的第一开关被接通以允许其电荷保持机构被充电。第一电流源的第二开关导通，以允许保留的保留电荷在第一输入上被断言。电荷打开第一个电流源的控制开关，电荷在第一个输入端被断言。接通第一电流源的电荷排放机构，之后允许电荷在电荷被断言之后以受控的方式排出。

5. 发明授权

US07286620B2 Equalizer for reduced intersymbol interference via partial clock switching 有权
标题翻译：均衡器通过部分时钟切换减少符号间干扰
公开(公告)号：US07286620B2
公开(公告)日：2007-10-23
申请号：US10665235
申请日：2003-09-17
申请人： Hayden C. Cranford, Jr. , Westerfield J. Ficken , Wentai Liu
发明人： Hayden C. Cranford, Jr. , Westerfield J. Ficken , Wentai Liu
IPC分类号： H04L1/00
CPC分类号： H04L25/03133
摘要： A method and system for is disclosed for reducing intersymbol interference in a stream of data bits to be transmitted over a transmission medium. Aspects of the present invention include a phase delayed clock generated from a reference clock that produces an edge on sub-bit boundaries; and a digital filter coupled to the phase delayed clock for performing equalization on the data bits, wherein the phase delayed clock causes the digital filter to perform partial clock switching, such that equalization is performed on the data bits on-sub-bit boundaries.
摘要翻译：公开了一种用于减少要在传输介质上传输的数据位流中的符号间干扰的方法和系统。本发明的方面包括从产生子位边界边缘的参考时钟产生的相位延迟时钟; 以及耦合到所述相位延迟时钟的数字滤波器，用于对所述数据位执行均衡，其中所述相位延迟时钟使所述数字滤波器执行部分时钟切换，使得对所述数据位在子位边界执行均衡。

6. 发明授权

US06897712B2 Apparatus and method for detecting loss of high-speed signal 有权
标题翻译：用于检测高速信号损耗的装置和方法
公开(公告)号：US06897712B2
公开(公告)日：2005-05-24
申请号：US10604799
申请日：2003-08-18
申请人： Westerfield J. Ficken , Louis L. Hsu , James S. Mason , Phil J. Murfet
发明人： Westerfield J. Ficken , Louis L. Hsu , James S. Mason , Phil J. Murfet
IPC分类号： G05F1/10 , H03K5/08 , H03K5/19 , H03K5/22 , H04L25/02 , H04L25/08
CPC分类号： H03K5/19 , H03K5/08 , H04L25/0272 , H04L25/085
摘要： An apparatus and method is provided for detecting loss of differential signal carried by a pair of differential signal lines. According to the method, a common mode level is detected from voltages on the pair of differential signal lines. A threshold level is generated, referenced to the detected common mode level. A signal level is generated from the voltages on the pair of differential signal lines, the signal level being averaged over a first period of time. From the threshold level and the detected common mode level a reference level is generated, the reference level being averaged over a second period of time longer than then the first period of time. The signal level is compared to the reference level to determine if a signal is present on the pair of differential signal lines.
摘要翻译：提供一种用于检测由一对差分信号线携带的差分信号的损耗的装置和方法。根据该方法，从该对差分信号线上的电压检测共模电平。产生阈值电平，参考检测到的共模电平。信号电平由一对差分信号线上的电压产生，信号电平在第一时间段内被平均化。从阈值电平和检测到的共模电平产生参考电平，在比第一时间段长的第二时间段内平均参考电平。将信号电平与参考电平进行比较，以确定信号对是否存在于该对差分信号线上。

7. 发明授权

US07940846B2 Test circuit for serial link receiver 有权
标题翻译：串行链路接收机测试电路
公开(公告)号：US07940846B2
公开(公告)日：2011-05-10
申请号：US11621016
申请日：2007-01-08
申请人： Hayden C. Cranford, Jr. , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
发明人： Hayden C. Cranford, Jr. , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
IPC分类号： H04B3/00
CPC分类号： G01R31/31715
摘要： A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.
摘要翻译：用于串行链路接收机的测试电路包括耦合到串行链路接收机的第一输入端的第一电流源和耦合到串行链路接收机的第二输入端的第二电流源。第一电流源与第二电流源对称地匹配。第一电流源的第一开关被接通以允许其电荷保持机构被充电。第一电流源的第二开关导通，以允许保留的保留电荷在第一输入上被断言。电荷打开第一个电流源的控制开关，电荷在第一个输入端被断言。接通第一电流源的电荷排放机构，之后允许电荷在电荷被断言之后以受控的方式排出。

8. 发明申请

US20080165837A1 TEST CIRCUIT FOR SERIAL LINK RECEIVER 有权
标题翻译：串行接收器测试电路
公开(公告)号：US20080165837A1
公开(公告)日：2008-07-10
申请号：US11621016
申请日：2007-01-08
申请人： Hayden C. Cranford , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
发明人： Hayden C. Cranford , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
IPC分类号： H04Q1/20 , H04B3/46 , H04B17/00
CPC分类号： G01R31/31715
摘要： A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.
摘要翻译：用于串行链路接收机的测试电路包括耦合到串行链路接收机的第一输入端的第一电流源和耦合到串行链路接收机的第二输入端的第二电流源。第一电流源与第二电流源对称地匹配。第一电流源的第一开关被接通以允许其电荷保持机构被充电。第一电流源的第二开关导通，以允许保留的保留电荷在第一输入上被断言。电荷打开第一个电流源的控制开关，电荷在第一个输入端被断言。接通第一电流源的电荷排放机构，之后允许电荷在电荷被断言之后以受控的方式排出。

9. 发明授权

US07289572B2 Method and system for scalable pre-driver to driver interface 有权
标题翻译：可扩展的预驱动程序到驱动程序接口的方法和系统
公开(公告)号：US07289572B2
公开(公告)日：2007-10-30
申请号：US10265755
申请日：2002-10-07
申请人： Hayden C. Cranford, Jr. , Westerfield J. Ficken
发明人： Hayden C. Cranford, Jr. , Westerfield J. Ficken
IPC分类号： H04L27/00
CPC分类号： H04L25/028 , H04L25/0272
摘要： A system and method for a predriver and driver interface having scalable output drive capability with corresponding scalable power is disclosed. The system includes a predriver to driver interface having a data source; a plurality of predrivers, each coupled to the data source and responsive to an enable signal, for driving a predriven data signal only when a corresponding enable signal is asserted and for consuming reduced power when the corresponding enable signal is deasserted; a plurality of drivers, each coupled to one of the plurality of predrivers to receive a corresponding predriven data signal from the corresponding predriver and responsive to the enable signal coupled to the corresponding predriver, for driving an output with the predriven data signal only when the corresponding enable signal is asserted and for consuming reduced power when the corresponding enable signal is deasserted; and a controller, coupled to the predrivers and the drivers, for selectively asserting the enable signals to provide variable output drive capability of the data source to the output while providing scalable power consumption.
摘要翻译：公开了一种具有可扩展输出驱动能力和相应的可扩展功率的预驱动器和驱动器接口的系统和方法。该系统包括具有数据源的驱动器接口的预驱动器; 每个耦合到数据源并且响应于使能信号的预驱动器，用于仅在相应的使能信号被断言时驱动预驱动数据信号，并且当相应的使能信号被无效时消耗降低的功率; 多个驱动器，每个驱动器耦合到所述多个预驱动器中的一个，以从相应的预驱动器接收相应的预驱动数据信号，并且响应于耦合到相应的预驱动器的使能信号，仅在相应的预驱动器驱动具有预驱动数据信号的输出时使能信号被断言并且当相应的使能信号被无效时消耗降低的功率; 以及耦合到预驱动器和驱动器的控制器，用于选择性地确定使能信号，以在提供可缩放功率消耗的同时向输出端提供数据源的可变输出驱动能力。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式