专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080159369A1 METHOD OF GENERATING AN EYE DIAGRAM OF INTEGRATED CIRCUIT TRANSMITTED SIGNALS 审中-公开
标题翻译：生成集成电路传输信号的眼图的方法
公开(公告)号：US20080159369A1
公开(公告)日：2008-07-03
申请号：US12049325
申请日：2008-03-15
申请人： Hayden C. Cranford , Fadi H. Gebara , Jeremy D. Schaub
发明人： Hayden C. Cranford , Fadi H. Gebara , Jeremy D. Schaub
IPC分类号： G06K9/68
CPC分类号： G01R31/31711 , H04L1/205 , H04L1/24
摘要： A sequence of K voltage samples of a transmitted data signal is generated by sampling, digitizing, and storing voltage samples of the data signal with an imbedded sample clock on an IC having an unknown period TS. The K voltage samples are plotted against a time base of K sequential times TB[K] normalized so all samples fall within one cycle of the data clock used to generate the data signal or a unit time of 1. The time base is generated by estimating the sample clock period TSE to be some multiple of 1/P where P is greater than K. Eye diagrams are analyzed for time jitter wherein only the minimum value of jitter is saved. TSE is incremented by 1/P until TS is greater than one half the data clock period. The eye diagram at the TSE with the minimum time jitter is used to analyze the data channels.
摘要翻译：通过在具有未知周期TS的IC上以嵌入的采样时钟采样，数字化和存储数据信号的电压采样来生成发送数据信号的K个电压样本的序列。 K电压样本相对于K次顺序TB [K]的时基绘制，归一化，所以所有采样都落在用于生成数据信号的数据时钟或单位时间为1的一个周期内。时基是通过估计采样时钟周期TSE为1 / P的某个倍数，其中P大于K.眼图分析时间抖动，其中只保存抖动的最小值。 TSE递增1 / P，直到TS大于数据时钟周期的一半。 TSE具有最小时间抖动的眼图用于分析数据通道。

2. 发明申请

US20080126010A1 METHOD AND APPARATUS FOR CONSTRUCTING A SYNCHRONOUS SIGNAL DIAGRAM FROM ASYNCHRONOUSLY SAMPLED DATA 失效
标题翻译：用于构建非同步采样数据同步信号图的方法和装置
公开(公告)号：US20080126010A1
公开(公告)日：2008-05-29
申请号：US11427860
申请日：2006-06-30
申请人： Hayden C. Cranford , Fadi H. Gebara , Jeremy D. Schaub
发明人： Hayden C. Cranford , Fadi H. Gebara , Jeremy D. Schaub
IPC分类号： G06F17/18 , G06F15/00
CPC分类号： H04L1/205 , G01R31/31709
摘要： A method a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronoulsy sampled (or alternatively a clock signal is latched). The data signal or a second signal is compared to a settable threshold voltage and sampled. The edge and comparison data are folded according to a swept timebase tofind a minimum jitter period. The crossing of the signal diagram edges is determined from a peak of a histogram of the folded edge data. A histogram of ratios of the sample values versus displacement from the position of the crossing location is generated for each threshold voltage. The technique is repeated over a range of settable threshold voltages. Then, the ratio counts are differentiated across the histograms with respect to threshold voltage, from which a signal diagram is populated.
摘要翻译：一种用于提供信号图的低成本和生产可集成技术的方法。数据信号被边缘检测和异步脉冲采样（或者时钟信号被锁存）。将数据信号或第二信号与可设置的阈值电压进行比较并采样。边缘和比较数据根据扫描时基折叠以获得最小抖动周期。信号图边缘的交叉由折叠边缘数据的直方图的峰值确定。对于每个阈值电压产生样本值与交叉位置位置之间的位移比率的直方图。该技术在可设置的阈值电压范围内重复。然后，相对于阈值电压，在直方图之间区分比率计数，从中填充信号图。

3. 发明申请

US20080177489A1 SYSTEM AND CIRCUIT FOR CONSTRUCTING A SYNCHRONOUS SIGNAL DIAGRAM FROM ASYNCHRONOUSLY SAMPLED DATA 有权
标题翻译：用于从非同步采样数据构建同步信号图的系统和电路
公开(公告)号：US20080177489A1
公开(公告)日：2008-07-24
申请号：US12055317
申请日：2008-03-26
申请人： Hayden C. Cranford , Fadi H. Gebara , Jeremy D. Schaub
发明人： Hayden C. Cranford , Fadi H. Gebara , Jeremy D. Schaub
IPC分类号： G01R13/00 , G06F17/18 , G01R29/26
CPC分类号： H04L1/205 , G01R31/31709
摘要： A system and circuit for constructing a synchronous signal diagram from asynchronous sampled data provides a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronously sampled (or alternatively a clock signal is latched). The data signal or a second signal is compared to a settable threshold voltage and sampled. The edge and comparison data are folded according to a swept timebase to find a minimum jitter period. The crossing of the signal diagram edges is determined from a peak of a histogram of the folded edge data. A histogram of ratios of the sample values versus displacement from the position of the crossing location is generated for each threshold voltage. The technique is repeated over a range of settable threshold voltages. Then, the ratio counts are differentiated across the histograms with respect to threshold voltage, from which a signal diagram is populated.
摘要翻译：用于从异步采样数据构建同步信号图的系统和电路为提供信号图提供了低成本和生产可集成技术。数据信号被边缘检测和异步采样（或者时钟信号被锁存）。将数据信号或第二信号与可设置的阈值电压进行比较并采样。边缘和比较数据根据扫描时基折叠以找到最小抖动周期。信号图边缘的交叉由折叠边缘数据的直方图的峰值确定。对于每个阈值电压产生样本值与交叉位置位置之间的位移比率的直方图。该技术在可设置的阈值电压范围内重复。然后，相对于阈值电压，在直方图之间区分比率计数，从中填充信号图。

4. 发明申请

US20080002762A1 A Method of Generating an Eye Diagram of Integrated Circuit Transmitted Signals 失效
标题翻译：一种产生集成电路传输信号眼图的方法
公开(公告)号：US20080002762A1
公开(公告)日：2008-01-03
申请号：US11427831
申请日：2006-06-30
申请人： Hayden C. Cranford , Fadi H. Gebara , Jeremy D. Schaub
发明人： Hayden C. Cranford , Fadi H. Gebara , Jeremy D. Schaub
IPC分类号： H04B3/46 , H04L7/00
CPC分类号： G01R31/31711 , H04L1/205 , H04L1/24
摘要： A sequence of K voltage samples of a transmitted data signal is generated by sampling, digitizing, and storing voltage samples of the data signal with an imbedded sample clock on an IC having an unknown period TS. The K voltage samples are plotted against a time base of K sequential times TB[K] normalized so all samples fall within one cycle of the data clock used to generate the data signal or a unit time of 1. The time base is generated by estimating the sample clock period TSE to be some multiple of 1/P where P is greater than K. Eye diagrams are analyzed for time jitter wherein only the minimum value of jitter is saved. TSE is incremented by 1/P until TS is greater than one half the data clock period. The eye diagram at the TSE with the minimum time jitter is used to analyze the data channels.
摘要翻译：通过在具有未知周期TS的IC上以嵌入的采样时钟采样，数字化和存储数据信号的电压采样来生成发送数据信号的K个电压样本的序列。 K电压样本相对于K次顺序TB [K]的时基绘制，归一化，所以所有采样都落在用于生成数据信号的数据时钟或单位时间为1的一个周期内。时基是通过估计采样时钟周期TSE为1 / P的某个倍数，其中P大于K.眼图分析时间抖动，其中只保存抖动的最小值。 TSE递增1 / P，直到TS大于数据时钟周期的一半。 TSE具有最小时间抖动的眼图用于分析数据通道。

5. 发明申请

US20080229265A1 Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees 审中-公开
标题翻译：用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法的设计结构
公开(公告)号：US20080229265A1
公开(公告)日：2008-09-18
申请号：US12129748
申请日：2008-05-30
申请人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F1/10 , G06F17/5045
摘要： Design structure for a clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a design structure for a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.
摘要翻译：公开了用于提供平衡负载的时钟分配网络，结构和方法的设计结构。特别地，用于时钟分配网络的设计结构可以由一个或多个时钟扇出分配电平形成。每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

6. 发明申请

US20080218201A1 CML DELAY CELL WITH LINEAR RAIL-TO-RAIL TUNING RANGE AND CONSTANT OUTPUT SWING 失效
公开(公告)号：US20080218201A1
公开(公告)日：2008-09-11
申请号：US12124384
申请日：2008-05-21
申请人： Hayden C. Cranford , Marcel A. Kossel , Thomas E. Morf
发明人： Hayden C. Cranford , Marcel A. Kossel , Thomas E. Morf
IPC分类号： H03K19/003
CPC分类号： H03K5/13 , H03K5/133 , H03K2005/00032 , H03K2005/00208
摘要： A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a current source I0, and a compensation circuit having switching point optimized inverters having a first plurality of transistors having a transconductance βpN and a second plurality of transistors having a transconductance βnN, wherein respective ratios of βnN/βpN determine an inverter switching point of respective switching point optimized inverters, the first and second plurality of transistors having gates coupled to the tuning voltage input of the CML delay cell, wherein the switching point optimized inverters are followed by weighted tail current sources M0N that supply additional currents to the current source I0 at a drain node of the third transistor.

7. 发明申请

US20080186051A1 FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH 有权
标题翻译：用于可配置混合逻辑信号分配路径的灵活多模态逻辑单元
公开(公告)号：US20080186051A1
公开(公告)日：2008-08-07
申请号：US11670537
申请日：2007-02-02
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/094
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路。特别地，示例性多模电路可以被配置为以全摆动模式，限制摆动模式，全摆幅至限定摆动转换器模式和限定摆动至全摆幅转换器模式之一进行操作。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

8. 发明授权

US07332932B2 Serial link receiver with wide input voltage range and tolerance to high power voltage supply 有权
标题翻译：具有宽输入电压范围的串行链路接收器和高电源电压容限
公开(公告)号：US07332932B2
公开(公告)日：2008-02-19
申请号：US11417626
申请日：2006-05-04
申请人： Hayden C. Cranford , Westerfield J. Ficken , David A. Freitas , Joseph M. Stevens
发明人： Hayden C. Cranford , Westerfield J. Ficken , David A. Freitas , Joseph M. Stevens
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0175
CPC分类号： H03F3/45475 , H03F1/52 , H03F3/45973 , H03F2203/45078 , H03F2203/45431 , H03F2203/45541 , H03F2203/45561 , H03F2203/45588
摘要： A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamplifier and a common mode feedback loop, which monitors shifts in the common mode voltage and adjusts the inputs provided to the preamplifier. The circuit device maintains a flat bandwidth to accommodate all signaling rates.
摘要翻译：一种用于设计串行链路接收机的电路装置和方法，其适应宽的输入电压范围并且提供对高终端电压的容限。接收机设计有一对连接在输入和前置放大器之间的RC网络和一个共模反馈环路，它监控共模电压的变化并调整提供给前置放大器的输入。电路设备保持平坦的带宽以适应所有信令速率。

9. 发明授权

US07315594B2 Clock data recovering system with external early/late input 失效
标题翻译：具有外部早/晚输入的时钟数据恢复系统
公开(公告)号：US07315594B2
公开(公告)日：2008-01-01
申请号：US10484608
申请日：2002-07-15
申请人： Martin Schmatz , Hayden C. Cranford , Vernon R. Norman
发明人： Martin Schmatz , Hayden C. Cranford , Vernon R. Norman
IPC分类号： H04L7/00
CPC分类号： H03L7/091 , H03L7/0814 , H03L7/089 , H04L7/0331
摘要： The invention is directed to a clock data recovery system for resampling a clock signal to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependant on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.
摘要翻译：本发明涉及一种用于将时钟信号重新采样到输入数据信号的时钟数据恢复系统。时钟数据恢复系统包括用于产生时钟信号的时钟发生器和用于根据相位调整控制信号产生采样相位的相位调整单元。它还包括可操作以产生输入样本流的数据采样单元和用于从其产生内部早期信号和内部迟滞信号的边缘检测器。设置相位调整控制单元，用于在早期信号的使用下产生相位调整控制信号，并且延迟信号。相位调整控制单元可以用外部早/晚信号进给，和/或包括用于传送出口早/晚信号的输出。

10. 发明申请

US20090033401A1 Level Shifting Circuit With Symmetrical Topology 审中-公开
标题翻译：具有对称拓扑的电平转换电路
公开(公告)号：US20090033401A1
公开(公告)日：2009-02-05
申请号：US11832699
申请日：2007-08-02
申请人： Marcel A. Kossel , Hayden C. Cranford
发明人： Marcel A. Kossel , Hayden C. Cranford
IPC分类号： H03L5/00
CPC分类号： H03K3/35613
摘要： A shifter circuit includes a pair of feed forward sections and a pair of feedback sections. The sections are arranged and coupled to form a balanced symmetrical topology. The feed forward sections each include inverter pairs of PMOS and NMOS devices. The feedback sections each include a pair of cross-coupled devices. A pair of output nodes are operatively positioned between the pair of feedback sections. A method for using the circuit to generate output signals at respective output ports is also disclosed.
摘要翻译：移位电路包括一对前馈部分和一对反馈部分。这些部分被布置和耦合以形成平衡的对称拓扑。前馈部分各自包括PMOS和NMOS器件的反相器对。反馈部分各自包括一对交叉耦合器件。一对输出节点可操作地位于该对反馈部分之间。还公开了一种在各个输出端口使用该电路产生输出信号的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式