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31. 发明申请

US20140087526A1 MULTI-GATE FIELD EFFECT TRANSISTOR DEVICES 审中-公开
标题翻译：多门场效应晶体管器件
公开(公告)号：US20140087526A1
公开(公告)日：2014-03-27
申请号：US13628251
申请日：2012-09-27
申请人： Veeraraghavan S. Basker , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： A method for fabricating a field effect transistor device includes patterning a semiconductor fin on a substrate insulator layer, the substrate insulator layer arranged on a substrate, patterning a dummy gate stack over a portion of the fin, forming spacers adjacent to the dummy gate stack, removing the dummy gate stack to form a cavity that exposes portions of the substrate insulator layer and the fin, removing exposed portions of the substrate insulator layer to increase a depth of the cavity, removing a region of the substrate insulator layer from beneath the fin to suspend a portion of the fin above the substrate insulator layer, forming a gate stack in the cavity, removing a portion of the gate stack in the cavity to expose a portion of a dielectric layer arranged on the fin, and depositing an insulator material in the cavity.
摘要翻译：一种用于制造场效应晶体管器件的方法，包括在衬底绝缘体层上图形化半导体鳍片，将衬底绝缘体层布置在衬底上，在鳍片的一部分上构图虚拟栅极堆叠，形成与虚拟栅极叠层相邻的间隔区，去除虚拟栅极堆叠以形成露出衬底绝缘体层和鳍的部分的空腔，去除衬底绝缘体层的暴露部分以增加空腔的深度，从衬底下方去除衬底绝缘体层的区域到悬挂在衬底绝缘体层上方的鳍片的一部分，在空腔中形成栅极叠层，去除空腔中的栅极叠层的一部分以暴露布置在鳍片上的电介质层的一部分，并将绝缘体材料沉积在腔。

32. 发明授权

US08674476B2 Anti-fuse device structure and electroplating circuit structure and method 有权
标题翻译：反熔丝器件结构及电镀电路结构及方法
公开(公告)号：US08674476B2
公开(公告)日：2014-03-18
申请号：US13535393
申请日：2012-06-28
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
摘要翻译：公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。在电沉积期间，可以选择性地控制通过电流路径的电流。此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。

33. 发明申请

US20140070294A1 FINFET TRENCH CIRCUIT 有权
标题翻译： FINFET TRENCH电路
公开(公告)号：US20140070294A1
公开(公告)日：2014-03-13
申请号：US13613684
申请日：2012-09-13
申请人： Jonathan E. Faltermeier , Veeraraghavan S. Basker , Kangguo Cheng , Theodorus Eduardus Standaert
发明人： Jonathan E. Faltermeier , Veeraraghavan S. Basker , Kangguo Cheng , Theodorus Eduardus Standaert
IPC分类号： H01L27/12 , H01L21/02
CPC分类号： H01L27/10829 , H01L21/845 , H01L27/10826 , H01L27/10832 , H01L27/10861 , H01L27/10867 , H01L27/10879 , H01L27/1207 , H01L27/1211 , H01L29/66181 , H01L29/945
摘要： A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.
摘要翻译：公开了一种finFET沟槽电路。 FinFET通过在沟槽导体的一部分上采用沟槽顶部氧化物与沟槽电容器集成。然后将通过栅极设置在沟槽顶部氧化物上方以形成更大的电路，例如DRAM阵列。通过利用多晶硅和单晶硅之间的不同生长速率形成沟槽顶部氧化物。

34. 发明授权

US08592290B1 Cut-very-last dual-EPI flow 有权
标题翻译：切割最后的双EPI流程
公开(公告)号：US08592290B1
公开(公告)日：2013-11-26
申请号：US13545456
申请日：2012-07-10
申请人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
发明人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
IPC分类号： H01L21/20
CPC分类号： H01L29/66795 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/6681
摘要： A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.
摘要翻译：描述了制造双外延FinFET的方法。该方法包括将第一外延材料添加到翅片阵列。该方法还包括使用第一掩蔽材料覆盖翅片阵列的至少第一部分并且从翅片阵列的未覆盖部分移除第一外延材料。在散热片阵列的未覆盖部分中的翅片上添加第二外延材料包括在该方法中。该方法还包括使用第二掩模材料覆盖翅片阵列的第二部分，并使用第一掩模材料和第二掩模材料执行定向蚀刻。还描述了装置和计算机程序产品。

35. 发明授权

US08551313B2 Method and apparatus for electroplating on soi and bulk semiconductor wafers 有权
标题翻译：用于电镀在硅和体半导体晶片上的方法和装置
公开(公告)号：US08551313B2
公开(公告)日：2013-10-08
申请号：US11940720
申请日：2007-11-15
申请人： Veeraraghavan S. Basker , Eduard Cartier , Hariklia Deligianni , Rajarao Jammy , Vamsi K. Paruchuri
发明人： Veeraraghavan S. Basker , Eduard Cartier , Hariklia Deligianni , Rajarao Jammy , Vamsi K. Paruchuri
IPC分类号： C25D5/02
CPC分类号： C25D5/18 , C25D5/024 , C25D17/001 , C25D17/002 , C25D17/005 , H01L21/2885 , H01L21/7624
摘要： An electroplating apparatus and method for depositing a metallic layer on the surface of a wafer is provided wherein said apparatus and method do not require physical attachment of an electrode to the wafer. The surface of the wafer to be plated is positioned to face the anode and a plating fluid is provided between the wafer and the electrodes to create localized metallic plating. The wafer may be positioned to physically separate and lie between the anode and cathode so that one side of the wafer facing the anode contains a catholyte solution and the other side of the wafer facing the cathode contains an anolyte solution. Alternatively, the anode and cathode may exist on the same side of the wafer in the same plating fluid. In one example, the anode and cathode are separated by a semi permeable membrane.
摘要翻译：提供了一种用于在晶片的表面上沉积金属层的电镀设备和方法，其中所述设备和方法不需要将电极物理附接到晶片。要镀覆的晶片的表面被定位成面对阳极，并且在晶片和电极之间设置电镀液以产生局部金属电镀。晶片可以被定位成物理分离并且位于阳极和阴极之间，使得面向阳极的晶片的一侧包含阴极电解液，并且晶片的面向阴极的另一侧包含阳极电解液。或者，阳极和阴极可以存在于同一电镀液中晶片的同一侧。在一个实例中，阳极和阴极被半透膜隔开。

36. 发明申请

US20130175594A1 INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC 有权
公开(公告)号：US20130175594A1
公开(公告)日：2013-07-11
申请号：US13551714
申请日：2012-07-18
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/12 , H01L21/782
CPC分类号： H01L21/84 , H01L27/10861 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L27/1108 , H01L27/1116 , H01L27/1203 , H01L29/945
摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.

37. 发明授权

US08368146B2 FinFET devices 有权
标题翻译： FinFET器件
公开(公告)号：US08368146B2
公开(公告)日：2013-02-05
申请号：US12815845
申请日：2010-06-15
申请人： Veeraraghavan S. Basker , David V. Horak , Hemanth Jagannathan , Charles W. Koburger, III
发明人： Veeraraghavan S. Basker , David V. Horak , Hemanth Jagannathan , Charles W. Koburger, III
IPC分类号： H01L21/70
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7845
摘要： A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures.
摘要翻译： FinFET结构及其制造方法具有降低的Ceff和增强的应力。 finFET结构包括多个finFET结构和形成栅极堆叠的一部分的应力材料，并且在多个finFET结构中的相邻空间之间的空间中。

38. 发明申请

US20120280250A1 SPACER AS HARD MASK SCHEME FOR IN-SITU DOPING IN CMOS FINFETS 失效
标题翻译：间隔器作为CMOS熔体中的现场掺杂的硬掩模方案
公开(公告)号：US20120280250A1
公开(公告)日：2012-11-08
申请号：US13100589
申请日：2011-05-04
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Sivananda K. Kanakasabapathy , Hemant Adhikari
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Sivananda K. Kanakasabapathy , Hemant Adhikari
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/336 , H01L29/78
CPC分类号： H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211
摘要： A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.
摘要翻译：一种制造半导体器件的方法，其包括至少两个翅片结构，其中所述至少两个翅片结构中的一个包括外延形成的原位掺杂的第二源极和漏极区域，其具有存在于鳍的侧壁上的刻面外侧壁结构体。在另一个实施例中，本发明还提供一种制造finFET的方法，其包括在鳍结构的侧壁中形成凹槽，并且在形成在鳍结构中的凹槽中外延形成延伸掺杂区域。还描述了通过上述方法形成的结构。

39. 发明授权

US08303791B2 Apparatus and method for electrochemical processing of thin films on resistive substrates 有权
标题翻译：电阻衬底薄膜电化学处理的装置和方法
公开(公告)号：US08303791B2
公开(公告)日：2012-11-06
申请号：US12198274
申请日：2008-08-26
申请人： Veeraraghavan S. Basker , John M. Cotte , Hariklia Deligianni , Matteo Flotta
发明人： Veeraraghavan S. Basker , John M. Cotte , Hariklia Deligianni , Matteo Flotta
IPC分类号： C25D7/12 , C25D5/00
CPC分类号： C25D5/54 , C25D5/006 , C25D5/02 , C25D7/123 , C25D11/005 , C25D11/024 , C25D17/001 , C25F3/14 , H01L21/28079 , H01L21/2885
摘要： An electrochemical process comprising: providing a 125 mm or larger semiconductor wafer in electrical contact with a conducting surface, wherein at least a portion of the semiconductor wafer is in contact with an electrolytic solution, said semiconductor wafer functioning as a first electrode; providing a second electrode in the electrolytic solution, the first and second electrode connected to opposite ends of an electric power source; and irradiating a surface of the semiconductor wafer with a light source as an electric current is applied across the first and the second electrodes. The invention is also directed to an apparatus including a light source and electrochemical components to conduct the electrochemical process.
摘要翻译：一种电化学方法，包括：提供与导电表面电接触的125mm或更大的半导体晶片，其中所述半导体晶片的至少一部分与电解液接触，所述半导体晶片用作第一电极; 在所述电解液中提供第二电极，所述第一和第二电极连接到电源的相对端; 并且在第一和第二电极之间施加用作为电流的光源照射半导体晶片的表面。本发明还涉及一种包括光源和用于进行电化学过程的电化学组分的设备。

40. 发明授权

US08242578B2 Anti-fuse device structure and electroplating circuit structure and method 有权
标题翻译：反熔丝器件结构及电镀电路结构及方法
公开(公告)号：US08242578B2
公开(公告)日：2012-08-14
申请号：US13072023
申请日：2011-03-25
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
IPC分类号： H01L23/52
CPC分类号： H01L23/5252 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
摘要翻译：公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。在电沉积期间，可以选择性地控制通过电流路径的电流。此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。

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