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1. 发明申请

US20130319613A1 CUT-VERY-LAST DUAL-EPI FLOW 有权
标题翻译：切割 - 最近的双EPI流程
公开(公告)号：US20130319613A1
公开(公告)日：2013-12-05
申请号：US13545456
申请日：2012-07-10
申请人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
发明人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
IPC分类号： H01L21/308
CPC分类号： H01L29/66795 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/6681
摘要： A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.
摘要翻译：描述了制造双外延FinFET的方法。该方法包括将第一外延材料添加到翅片阵列。该方法还包括使用第一掩蔽材料覆盖翅片阵列的至少第一部分并且从翅片阵列的未覆盖部分移除第一外延材料。在散热片阵列的未覆盖部分中的翅片上添加第二外延材料包括在该方法中。该方法还包括使用第二掩模材料覆盖翅片阵列的第二部分，并使用第一掩模材料和第二掩模材料执行定向蚀刻。还描述了装置和计算机程序产品。

2. 发明授权

US08569152B1 Cut-very-last dual-epi flow 有权
标题翻译：切割最后的双面流
公开(公告)号：US08569152B1
公开(公告)日：2013-10-29
申请号：US13487413
申请日：2012-06-04
申请人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E Standaert , Tenko Yamashita
发明人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E Standaert , Tenko Yamashita
IPC分类号： H01L21/20
CPC分类号： H01L29/66795 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/6681
摘要： A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.
摘要翻译：描述了制造双外延FinFET的方法。该方法包括将第一外延材料添加到翅片阵列。该方法还包括使用第一掩蔽材料覆盖翅片阵列的至少第一部分并且从翅片阵列的未覆盖部分移除第一外延材料。在散热片阵列的未覆盖部分中的翅片上添加第二外延材料包括在该方法中。该方法还包括使用第二掩模材料覆盖翅片阵列的第二部分，并使用第一掩模材料和第二掩模材料执行定向蚀刻。还描述了装置和计算机程序产品。

3. 发明授权

US08592290B1 Cut-very-last dual-EPI flow 有权
标题翻译：切割最后的双EPI流程
公开(公告)号：US08592290B1
公开(公告)日：2013-11-26
申请号：US13545456
申请日：2012-07-10
申请人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
发明人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
IPC分类号： H01L21/20
CPC分类号： H01L29/66795 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/6681
摘要： A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.
摘要翻译：描述了制造双外延FinFET的方法。该方法包括将第一外延材料添加到翅片阵列。该方法还包括使用第一掩蔽材料覆盖翅片阵列的至少第一部分并且从翅片阵列的未覆盖部分移除第一外延材料。在散热片阵列的未覆盖部分中的翅片上添加第二外延材料包括在该方法中。该方法还包括使用第二掩模材料覆盖翅片阵列的第二部分，并使用第一掩模材料和第二掩模材料执行定向蚀刻。还描述了装置和计算机程序产品。

4. 发明授权

US08546203B1 Semiconductor structure having NFET extension last implants 有权
标题翻译：具有NFET延伸最后植入物的半导体结构
公开(公告)号：US08546203B1
公开(公告)日：2013-10-01
申请号：US13551100
申请日：2012-07-17
申请人： Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Nicolas Loubet , Amlan Majumdar , Stefan Schmitz
发明人： Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Nicolas Loubet , Amlan Majumdar , Stefan Schmitz
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L29/66628
摘要： Method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. Low quality nitride and high quality nitride are formed on the semiconductor structure. The high quality nitride in the NFET portion is damaged by ion implantation to facilitate its removal. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The high quality nitride in the PFET portion is damaged by ion implantation to facilitate its removal. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.
摘要翻译：形成半导体结构的方法包括具有PFET部分和NFET部分的极薄的绝缘上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，与 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。在半导体结构上形成低质量的氮化物和高质量的氮化物。 NFET部分中的高质量氮化物被离子注入损坏以便于其去除。在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的高质量氮化物被离子注入损坏以便于其去除。扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

5. 发明授权

US08703550B2 Dual shallow trench isolation liner for preventing electrical shorts 有权
标题翻译：双浅沟槽隔离衬垫，用于防止电气短路
公开(公告)号：US08703550B2
公开(公告)日：2014-04-22
申请号：US13525642
申请日：2012-06-18
申请人： Bruce B. Doris , Shom Ponoth , Prasanna Khare , Qing Liu , Nicolas Loubet , Maud Vinet
发明人： Bruce B. Doris , Shom Ponoth , Prasanna Khare , Qing Liu , Nicolas Loubet , Maud Vinet
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/76879 , H01L21/0217 , H01L21/76224 , H01L21/76283 , H01L21/76802 , H01L21/76877 , H01L21/76897 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/41783 , H01L29/66545 , H01L29/6656 , H01L29/66568 , H01L29/66628 , H01L29/78609
摘要： A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.
摘要翻译：形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。随后形成栅极结构和源极/漏极结构。氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。

6. 发明申请

US20130334651A1 DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS 有权
标题翻译：用于防止电气短路的双层防爆隔离衬套
公开(公告)号：US20130334651A1
公开(公告)日：2013-12-19
申请号：US13525642
申请日：2012-06-18
申请人： Bruce B. Doris , Shom Ponoth , Prasanna Khare , Qing Liu , Nicolas Loubet , Maud Vinet
发明人： Bruce B. Doris , Shom Ponoth , Prasanna Khare , Qing Liu , Nicolas Loubet , Maud Vinet
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76879 , H01L21/0217 , H01L21/76224 , H01L21/76283 , H01L21/76802 , H01L21/76877 , H01L21/76897 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/41783 , H01L29/66545 , H01L29/6656 , H01L29/66568 , H01L29/66628 , H01L29/78609
摘要： A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.
摘要翻译：形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。随后形成栅极结构和源极/漏极结构。氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。

7. 发明授权

US09768055B2 Isolation regions for SOI devices 有权
公开(公告)号：US09768055B2
公开(公告)日：2017-09-19
申请号：US13590836
申请日：2012-08-21
申请人： Qing Liu , Nicolas Loubet , Prasanna Khare , Shom Ponoth , Maud Vinet , Bruce Doris
发明人： Qing Liu , Nicolas Loubet , Prasanna Khare , Shom Ponoth , Maud Vinet , Bruce Doris
IPC分类号： H01L21/76 , H01L21/762 , H01L29/66 , H01L29/786
CPC分类号： H01L21/76232 , H01L29/66772 , H01L29/78654
摘要： An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

8. 发明授权

US09070709B2 Method for producing a field effect transistor with implantation through the spacers 有权
标题翻译：用于通过间隔物注入的场效应晶体管的制造方法
公开(公告)号：US09070709B2
公开(公告)日：2015-06-30
申请号：US14119395
申请日：2011-06-09
申请人： Nicolas Posseme , Laurent Grenouillet , Yannick Le Tiec , Nicolas Loubet , Maud Vinet
发明人： Nicolas Posseme , Laurent Grenouillet , Yannick Le Tiec , Nicolas Loubet , Maud Vinet
IPC分类号： H01L29/66 , H01L21/8234 , H01L21/84 , H01L21/265
CPC分类号： H01L29/66477 , H01L21/2652 , H01L21/26586 , H01L21/823418 , H01L21/84 , H01L29/66545 , H01L29/66628 , H01L29/66772
摘要： The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.
摘要翻译：基板依次包括支撑基板，电绝缘层，半导体材料层和栅极图案。半导体材料层和栅极图案被覆盖层覆盖。第一掺杂杂质通过覆盖层注入到半导体材料层中，以将第一掺杂杂质的最大浓度的厚度置于第一层中。覆盖层被部分地消除，以形成离开源极/漏电极的横向间隔物。

9. 发明授权

US08900973B2 Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusion 有权
标题翻译：通过植入和热扩散使得FinFET结构中的压应变应变pFET通道的方法
公开(公告)号：US08900973B2
公开(公告)日：2014-12-02
申请号：US13221198
申请日：2011-08-30
申请人： Nathaniel C. Berliner , Pranita Kulkarni , Nicolas Loubet , Kingsuk Maitra , Sanjay C. Mehta , Paul A. Ronsheim , Toyoji Yamamoto , Zhengmao Zhu
发明人： Nathaniel C. Berliner , Pranita Kulkarni , Nicolas Loubet , Kingsuk Maitra , Sanjay C. Mehta , Paul A. Ronsheim , Toyoji Yamamoto , Zhengmao Zhu
IPC分类号： H01L21/326 , H01L21/84 , H01L27/12 , H01L29/78
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/7848
摘要： A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.
摘要翻译：制造半导体器件的方法在pFET区域中形成第一鳍，并且在nFET区域中形成第二鳍。包含应变材料的多个保形微层沉积在第一和第二鳍片上。在第一翅片上形成保护盖材料，并且从第二翅片选择性地去除保形层。然后将应变材料热扩散到第一鳍中。在热退火之后以及在从第二散热片选择性地去除保形微层之后，从第一散热片上去除保护帽材料。

10. 发明申请

US20140087524A1 METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR WITH IMPLANTATION THROUGH THE SPACERS 有权
标题翻译：用于产生具有通过间隔物移植的场效应晶体管的方法
公开(公告)号：US20140087524A1
公开(公告)日：2014-03-27
申请号：US14119395
申请日：2011-06-09
申请人： Nicolas Posseme , Laurent Grenouillet , Yannick Le Tiec , Nicolas Loubet , Maud Vinet
发明人： Nicolas Posseme , Laurent Grenouillet , Yannick Le Tiec , Nicolas Loubet , Maud Vinet
IPC分类号： H01L29/66
CPC分类号： H01L29/66477 , H01L21/2652 , H01L21/26586 , H01L21/823418 , H01L21/84 , H01L29/66545 , H01L29/66628 , H01L29/66772
摘要： The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.
摘要翻译：基板依次包括支撑基板，电绝缘层，半导体材料层和栅极图案。半导体材料层和栅极图案被覆盖层覆盖。第一掺杂杂质通过覆盖层注入到半导体材料层中，以将第一掺杂杂质的最大浓度的厚度置于第一层中。覆盖层被部分地消除，以形成离开源极/漏电极的横向间隔物。

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