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31. 发明申请

US20060231750A1 Image sensor module package 审中-公开
标题翻译：图像传感器模块包装
公开(公告)号：US20060231750A1
公开(公告)日：2006-10-19
申请号：US11364324
申请日：2006-03-01
申请人： Yeong-Ching Chao , An-Hong Liu , Hsiang-Ming Huang , Yi-Chang Lee , Yao-Jung Lee
发明人： Yeong-Ching Chao , An-Hong Liu , Hsiang-Ming Huang , Yi-Chang Lee , Yao-Jung Lee
IPC分类号： H01J5/02
CPC分类号： H01L27/14618 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： An image sensor module package is disclosed. A plurality of connecting pads are formed on a first surface of a glass substrate having and located outside a light entering area. A via-redistribution layer is formed on an opposing second surface of the glass substrate. A plurality of vias penetrate the glass substrate to electrically connect the via-redistribution layer with the connecting pads. A bumped image sensor chip is flip-chip attached to the second surface of the glass substrate so that a sensing area of the image sensor chip is corresponding to a light entering area of the glass substrate without blocking the via-redistribution layer. The connecting pads may connect to a plurality of solder balls or a FPC. In one embodiment, a plurality of passive components can be placed on the via-redistribution layer to enhance the electrical performance and the functions of the image sensor module package.
摘要翻译：公开了一种图像传感器模块封装。在具有并位于光进入区域外的玻璃基板的第一表面上形成多个连接焊盘。通孔再分配层形成在玻璃基板的相对的第二表面上。多个通孔穿透玻璃基板以将通孔再分配层与连接垫电连接。将碰撞的图像传感器芯片倒装安装在玻璃基板的第二表面上，使得图像传感器芯片的感测区域对应于玻璃基板的光进入区域而不阻塞通路再分配层。连接焊盘可以连接到多个焊球或FPC。在一个实施例中，可以将多个无源部件放置在通孔再分配层上，以增强图像传感器模块封装的电性能和功能。

32. 发明申请

US20060043538A1 Bump structure of an opto-electronic chip 审中-公开
标题翻译：凹凸结构的光电芯片
公开(公告)号：US20060043538A1
公开(公告)日：2006-03-02
申请号：US11208595
申请日：2005-08-23
申请人： Yi-Chang Lee , An-Hong Liu , Yeong-Ching Chao , Yao-Jung Lee
发明人： Yi-Chang Lee , An-Hong Liu , Yeong-Ching Chao , Yao-Jung Lee
IPC分类号： H01L23/58 , H01L23/02
CPC分类号： H01L27/14636 , H01L24/10 , H01L2224/05001 , H01L2224/05022 , H01L2224/05567 , H01L2224/05572 , H01L2224/05573 , H01L2224/05624 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/00014
摘要： An opto-electronic chip includes a plurality of multi-level bumps thereon, each consisting of multiple plated layers. The opto-electronic chip has a plurality of bonding pads and an photoelectric effecting region on its active surface. Each multi-level bump comprises at least an electroless-plated nickel (Ni) layer and an electroless-plated gold (Au) layer wherein the nickel layers cover the bonding pads and the gold layers are formed on the tops of the nickel layers. Furthermore, the thickness of the nickel layers is larger than that of the gold layers. The UBM processes in conventional bumping processes are not needed so that the contaminations or damages to the photoelectric effecting region of the opto-electronic chip due to UBM can be eliminated.
摘要翻译：光电芯片包括多个多层凸起，每个由多个镀层组成。光电芯片在其有源表面上具有多个接合焊盘和光电效应区域。每个多级凸块包括至少一种无电镀镍（Ni）层和无电镀金（Au）层，其中镍层覆盖接合焊盘，并且金层形成在镍层的顶部上。此外，镍层的厚度大于金层的厚度。常规碰撞过程中的UBM工艺不需要，可以消除由UBM引起的光电芯片光电效应区域的污染或损坏。

33. 发明申请

US20060022317A1 Chip-under-tape package structure and manufacture thereof 审中-公开
标题翻译：芯片下带封装结构及其制造
公开(公告)号：US20060022317A1
公开(公告)日：2006-02-02
申请号：US11180494
申请日：2005-07-13
申请人： An-Hong Liu , Chao Ching , Yao Lee , Yi-Chang Lee , Hsiang-Ming Huang
发明人： An-Hong Liu , Chao Ching , Yao Lee , Yi-Chang Lee , Hsiang-Ming Huang
IPC分类号： H01L21/50 , H01L23/495
CPC分类号： H01L23/3114 , H01L23/13 , H01L24/48 , H01L24/97 , H01L2224/32225 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/73204 , H01L2224/73215 , H01L2924/00014 , H01L2924/01322 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The invention discloses a chip-under-tape package structure including a flexible substrate, a chip, a plurality of connecting members, a plurality of stud bumps, and a potting adhesive. The flexible substrate includes a plurality of inner pads and a plurality of outer pads. The chip is attached to a lower surface of the flexible substrate and has an active surface thereon providing a plurality of bonding pads which each corresponds to one of the inner pads. Each of the connecting members functions electrically connecting one of the bonding pads with the inner pad corresponding to said one bonding pad. Each of the stud bumps is attached to one of the outer pads. The potting adhesive is coated to seal the connecting members. Accordingly, the invention is capable of preventing the outer pads from being contaminated by the potting adhesive and suitable for low-cost package of high frequency memory chip.
摘要翻译：本发明公开了一种包括柔性基板，芯片，多个连接部件，多个螺柱凸块和灌封粘合剂的芯片下带封装结构。柔性基板包括多个内垫和多个外垫。芯片附接到柔性基板的下表面并且在其上具有有源表面，其上提供多个键合焊盘，每个焊盘对应于内部焊盘之一。每个连接构件使一个接合焊盘与相应于所述一个焊盘的内焊盘电连接。每个螺柱凸块连接到外垫之一。涂覆粘合剂以密封连接构件。因此，本发明能够防止外垫被灌封粘合剂污染，并且适用于低成本的高频存储芯片封装。

34. 发明申请

US20070235871A1 High frequency IC package and method for fabricating the same 有权
标题翻译：高频IC封装及其制造方法
公开(公告)号：US20070235871A1
公开(公告)日：2007-10-11
申请号：US11400182
申请日：2006-04-10
申请人： Hsiang-Ming Huang , An-Hong Liu , Yeong-Jyh Lin , Yi-Chang Lee , Wu-Chang Tu , Chun-Hung Lin , Shih Chiu
发明人： Hsiang-Ming Huang , An-Hong Liu , Yeong-Jyh Lin , Yi-Chang Lee , Wu-Chang Tu , Chun-Hung Lin , Shih Chiu
IPC分类号： H01L23/48
CPC分类号： H01L24/10 , H01L23/13 , H01L23/3114 , H01L23/49816 , H01L24/06 , H01L24/13 , H01L24/48 , H01L24/81 , H01L24/83 , H01L24/90 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/13 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2224/8121 , H01L2224/81815 , H01L2224/83194 , H01L2224/838 , H01L2224/9202 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the substrate in a manner that the bumps are inserted into the bump holes respectively. The conductive fillers are formed in the bump holes to electrically connect the bumps to the circuit layer of the substrate. The high frequency IC package has a shorter electrical path and a thinner package thickness.
摘要翻译：高频IC封装主要包括衬底，凸起芯片和多个导电填料，其中衬底具有从顶表面到底表面穿透的多个凸起孔。芯片的有源表面以分别插入到凸块孔中的方式附接到基板的顶表面。导电填料形成在凸起孔中，以将凸块电连接到基板的电路层。高频IC封装具有更短的电路径和更薄的封装厚度。

35. 发明申请

US20070080452A1 Bump structure and its forming method 审中-公开
标题翻译：凹凸结构及其成型方法
公开(公告)号：US20070080452A1
公开(公告)日：2007-04-12
申请号：US11514329
申请日：2006-09-01
申请人： Chen-Ya- Chi , Chun-Ying Lin , An-Hong Liu , Yi-Chang Lee , Hsiang-Ming Huang
发明人： Chen-Ya- Chi , Chun-Ying Lin , An-Hong Liu , Yi-Chang Lee , Hsiang-Ming Huang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/44
CPC分类号： H01L24/10 , H01L24/13 , H01L2224/05571 , H01L2224/05573 , H01L2224/13 , H01L2224/13099 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/351 , H05K3/4007 , H05K3/4015 , H05K2201/0347 , H05K2201/0367 , H05K2201/10977 , H05K2203/049 , H05K2203/0597 , H01L2924/00 , H01L2224/05599
摘要： A bump structure mainly includes a metal core, a buffer encapsulant, and a metal cap where the metal core is a stud bump formed by wire bonding. The buffer encapsulant encapsulates the metal core. A metal cap is formed on the top surface of the buffer encapsulant and is electrically connected to the metal core. Therefore, the bump structure possesses excellent resistance of thermal stress to reduce or even eliminate metal fatigue in the bump without causing electrical shorts in the package.
摘要翻译：凸块结构主要包括金属芯，缓冲密封剂和金属盖，其中金属芯是通过引线键合形成的柱形凸块。缓冲密封剂封装金属芯。金属盖形成在缓冲密封剂的顶表面上并与金属芯电连接。因此，凸块结构具有优异的热应力阻力，以减少或甚至消除凸块中的金属疲劳，而不会导致封装中的电短路。

36. 发明申请

US20070069749A1 Method for fabricating a plurality of elastic probes in a row 审中-公开
标题翻译：一排制造多个弹性探针的方法
公开(公告)号：US20070069749A1
公开(公告)日：2007-03-29
申请号：US11605442
申请日：2006-11-29
申请人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
发明人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
IPC分类号： G01R31/02
CPC分类号： G01R3/00 , G01R1/06716 , G01R1/06744 , G01R1/07342 , H01R13/2414 , H01R43/007 , Y10T29/49147 , Y10T29/49155 , Y10T29/49204 , Y10T29/49222
摘要： A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.
摘要翻译：公开了一排形成多个弹性探针的方法。首先，提供基板，然后在基板上形成成形层，以便平行地提供两个平坦表面。在基板上和形成层上形成光致抗蚀剂层。然后，对光致抗蚀剂层进行图案化以形成与两个平坦表面之间的界面交叉的多个槽，其中在槽中形成有多个弹性探针。在一个实施例中，界面是成形层的边缘斜率，使得每个弹性探针具有至少一个弹性弯曲部分。在芯片探测期间，由于过驱动导致的弹性探针的移动方向垂直于接合焊盘的布置方向，使得弹性探头适用于探测具有高密度和细间距接合焊盘的芯片。

37. 发明申请

US20070046501A1 Electromagnetic coupling galvanic isolated digital output circuit with output feedback 失效
标题翻译：电磁耦合电隔离数字输出电路，具有输出反馈
公开(公告)号：US20070046501A1
公开(公告)日：2007-03-01
申请号：US11215516
申请日：2005-08-30
申请人： Chun-Hsiao Wang , Yi-Chang Lee
发明人： Chun-Hsiao Wang , Yi-Chang Lee
IPC分类号： H03M1/22
CPC分类号： H02M3/33523
摘要： A galvanic isolated digital output circuit of a digital system is provided herein, which utilizes an electromagnetic coupling device for galvanically isolating the system side and the output side of the digital output circuit. The digital output circuit contains a system-side driving circuit, an electromagnetic coupling device, and an output-side control circuit. The electromagnetic coupling device contains at least a system-side electromagnetic coupling element, a first output-side electromagnetic coupling element, and a second output-side electromagnetic coupling element. The system-side driving circuit is connected to the system-side electromagnetic coupling element, and takes the ON/OFF digital control signals from the digital system as input to turn on and off its driving to the system-side electromagnetic coupling element. The electromagnetic coupling device converts and transmits the electrical energy from the system side to the output side and thereby provides the working energy to and required by the output control circuit connected to the first output-side electromagnetic coupling element. The second output-side electromagnetic coupling element forms a feedback circuit, through which the electrical status at the output side is fed back to the system side via the electromagnetic coupling device.
摘要翻译：本文提供了一种数字系统的电隔离数字输出电路，其利用电磁耦合装置来电隔离数字输出电路的系统侧和输出侧。数字输出电路包括系统侧驱动电路，电磁耦合装置和输出侧控制电路。电磁耦合装置至少包括系统侧电磁耦合元件，第一输出侧电磁耦合元件和第二输出侧电磁耦合元件。系统侧驱动电路连接到系统侧电磁耦合元件，并将来自数字系统的ON / OFF数字控制信号作为输入，将其驱动接通和断开到系统侧电磁耦合元件。电磁耦合装置将电能从系统侧转换并传输到输出侧，从而提供与连接到第一输出侧电磁耦合元件的输出控制电路所需的工作能量。第二输出侧电磁耦合元件形成反馈电路，通过该反馈电路，输出侧的电气状态通过电磁耦合装置反馈到系统侧。

38. 发明申请

US20060267607A1 Method for fabricating a plurality of elastic probes in a row 有权
公开(公告)号：US20060267607A1
公开(公告)日：2006-11-30
申请号：US11364330
申请日：2006-03-01
申请人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
发明人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
IPC分类号： G01R31/02
CPC分类号： G01R3/00 , G01R1/06716 , G01R1/06744 , G01R1/07342 , H01R13/2414 , H01R43/007 , Y10T29/49147 , Y10T29/49155 , Y10T29/49204 , Y10T29/49222
摘要： A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.

39. 发明申请

US20060042834A1 Electronic device with a warped spring connector 有权
标题翻译：具有翘曲弹簧连接器的电子设备
公开(公告)号：US20060042834A1
公开(公告)日：2006-03-02
申请号：US11188860
申请日：2005-07-26
申请人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Yao-Jung Lee
发明人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Yao-Jung Lee
IPC分类号： H01R12/04 , H05K1/09
CPC分类号： H01L24/72 , G01R1/06727 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/3025 , H01L2924/351 , H01R13/2407 , H05K1/0216 , H05K3/4092 , H01L2924/00
摘要： An electronic device comprises a substrate and at least a warped spring connector. The substrate has a signal bonding pad and a ground plane. The warped spring connector is disposed on the substrate and is connected to the bonding pad. The warped spring connector includes at least a ground lead electrically connected to the ground plane, a dielectric layer on the ground lead, and a transmitting lead on the dielectric layer. The transmitting lead is bonded to the bonding pad. The ground lead is isolated from and close to the transmitting lead to solve cross-talk and noise problem. Furthermore, the coefficient of thermal expansion of the transmitting lead is different from that of the dielectric layer or the ground lead such that the warped spring connector has a suspending end suspending away from the substrate.
摘要翻译：电子设备包括基板和至少一个翘曲的弹簧连接器。衬底具有信号焊盘和接地层。翘曲弹簧连接器设置在基板上并连接到接合垫。翘曲弹簧连接器至少包括电连接到接地平面的接地引线，接地引线上的电介质层和介电层上的传输引线。传输引线接合到焊盘。接地线与发射线隔离并靠近发射线，以解决串扰和噪声问题。此外，传输引线的热膨胀系数与电介质层或接地引线的热膨胀系数不同，使得翘曲弹簧连接器具有悬挂远离基板的悬挂端。

40. 发明申请

US20110291267A1 Semiconductor wafer structure and multi-chip stack structure 审中-公开
标题翻译：半导体晶圆结构和多芯片堆叠结构
公开(公告)号：US20110291267A1
公开(公告)日：2011-12-01
申请号：US12856754
申请日：2010-08-16
申请人： David Wei Wang , An-Hong Liu , Hsiang-Ming Huang , Yi-Chang Lee
发明人： David Wei Wang , An-Hong Liu , Hsiang-Ming Huang , Yi-Chang Lee
IPC分类号： H01L23/498
CPC分类号： H01L23/481 , H01L21/563 , H01L21/76898 , H01L24/03 , H01L24/04 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05655 , H01L2224/05666 , H01L2224/06181 , H01L2224/11462 , H01L2224/11464 , H01L2224/13022 , H01L2224/13025 , H01L2224/13111 , H01L2224/13144 , H01L2224/13155 , H01L2224/1319 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/73204 , H01L2224/81193 , H01L2224/9202 , H01L2224/92125 , H01L2224/94 , H01L2225/06513 , H01L2225/06544 , H01L2924/0002 , H01L2924/01019 , H01L2924/14 , H01L2924/1461 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface. Hence, the reliability of multi-chip stack package structure can be enhanced with the application of these soft metal caps.
摘要翻译：半导体晶片结构包括第一表面和与第一表面相对的第二表面，形成在第一表面上的多个芯片区域，多个通孔形成在多个芯片区域中的每一个中，所述多个芯片区域连接第一表面和第二表面和形成在每个贯通硅孔中的贯通硅通孔（TSV）电极结构。每个贯通硅通孔电极结构包括形成在通孔的内壁上的电介质层，形成在电介质层的内壁上并在其中限定空位的阻挡层，填充到空位中的填充金属层，所述填充金属层的第一端低于形成凹部的第一表面;以及连接到所述填充金属层的第一端并覆盖所述填充金属层的第一端的软金属帽，其中所述软金属帽的一部分形成在所述凹部并且软金属帽从第一表面突出。因此，通过应用这些软金属盖，可以提高多芯片堆叠封装结构的可靠性。

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