专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060231750A1 Image sensor module package 审中-公开
标题翻译：图像传感器模块包装
公开(公告)号：US20060231750A1
公开(公告)日：2006-10-19
申请号：US11364324
申请日：2006-03-01
申请人： Yeong-Ching Chao , An-Hong Liu , Hsiang-Ming Huang , Yi-Chang Lee , Yao-Jung Lee
发明人： Yeong-Ching Chao , An-Hong Liu , Hsiang-Ming Huang , Yi-Chang Lee , Yao-Jung Lee
IPC分类号： H01J5/02
CPC分类号： H01L27/14618 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： An image sensor module package is disclosed. A plurality of connecting pads are formed on a first surface of a glass substrate having and located outside a light entering area. A via-redistribution layer is formed on an opposing second surface of the glass substrate. A plurality of vias penetrate the glass substrate to electrically connect the via-redistribution layer with the connecting pads. A bumped image sensor chip is flip-chip attached to the second surface of the glass substrate so that a sensing area of the image sensor chip is corresponding to a light entering area of the glass substrate without blocking the via-redistribution layer. The connecting pads may connect to a plurality of solder balls or a FPC. In one embodiment, a plurality of passive components can be placed on the via-redistribution layer to enhance the electrical performance and the functions of the image sensor module package.
摘要翻译：公开了一种图像传感器模块封装。在具有并位于光进入区域外的玻璃基板的第一表面上形成多个连接焊盘。通孔再分配层形成在玻璃基板的相对的第二表面上。多个通孔穿透玻璃基板以将通孔再分配层与连接垫电连接。将碰撞的图像传感器芯片倒装安装在玻璃基板的第二表面上，使得图像传感器芯片的感测区域对应于玻璃基板的光进入区域而不阻塞通路再分配层。连接焊盘可以连接到多个焊球或FPC。在一个实施例中，可以将多个无源部件放置在通孔再分配层上，以增强图像传感器模块封装的电性能和功能。

2. 发明授权

US07316065B2 Method for fabricating a plurality of elastic probes in a row 有权
标题翻译：一排制造多个弹性探针的方法
公开(公告)号：US07316065B2
公开(公告)日：2008-01-08
申请号：US11364330
申请日：2006-03-01
申请人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
发明人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
IPC分类号： G01R3/00
CPC分类号： G01R3/00 , G01R1/06716 , G01R1/06744 , G01R1/07342 , H01R13/2414 , H01R43/007 , Y10T29/49147 , Y10T29/49155 , Y10T29/49204 , Y10T29/49222
摘要： A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.
摘要翻译：公开了一排形成多个弹性探针的方法。首先，提供基板，然后在基板上形成成形层，以便平行地提供两个平坦表面。在基板上和形成层上形成光致抗蚀剂层。然后，对光致抗蚀剂层进行图案化以形成与两个平坦表面之间的界面交叉的多个槽，其中在槽中形成有多个弹性探针。在一个实施例中，界面是成形层的边缘斜率，使得每个弹性探针具有至少一个弹性弯曲部分。在芯片探测期间，由于过驱动导致的弹性探针的移动方向垂直于接合焊盘的布置方向，使得弹性探头适用于探测具有高密度和细间距接合焊盘的芯片。

3. 发明申请

US20060231941A1 Pillar grid array package 有权
标题翻译：支柱网格阵列包
公开(公告)号：US20060231941A1
公开(公告)日：2006-10-19
申请号：US11228234
申请日：2005-09-19
申请人： Hsiang-Ming Huang , Yeong-Ching Chao , Yi-Chang Lee , An-Hong Liu
发明人： Hsiang-Ming Huang , Yeong-Ching Chao , Yi-Chang Lee , An-Hong Liu
IPC分类号： H01L23/24 , H01L23/52
CPC分类号： H01L21/4853 , H01L21/563 , H01L23/13 , H01L23/3114 , H01L23/3128 , H01L23/49811 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/16225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/4824 , H01L2224/48472 , H01L2224/73204 , H01L2224/73215 , H01L2224/85181 , H01L2224/92147 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/01322 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/05599 , H01L2224/0401
摘要： A pillar grid array package (PGA) includes a substrate, a chip disposed on top of the substrate, and a plurality of stud bumps disposed on bottom of the substrate. The stud bumps are formed in an array and each has a flattened top to electrically connect to a printed circuit board, PCB, by an anisotropic conductive paste to achieve a thin package and to avoid substrate warpage problems of a ball grid array (BGA) during high-temperature reflow processes.
摘要翻译：支柱阵列封装（PGA）包括衬底，设置在衬底顶部的芯片和设置在衬底底部的多个柱形凸块。柱形凸起形成为阵列，并且每个具有平坦的顶部，以通过各向异性导电膏电连接到印刷电路板PCB，以实现薄的封装并避免球栅阵列（BGA）的基板翘曲问题高温回流工艺。

4. 发明授权

US07368809B2 Pillar grid array package 有权
标题翻译：支柱网格阵列包
公开(公告)号：US07368809B2
公开(公告)日：2008-05-06
申请号：US11228234
申请日：2005-09-19
申请人： Hsiang-Ming Huang , Yeong-Ching Chao , Yi-Chang Lee , An-Hong Liu
发明人： Hsiang-Ming Huang , Yeong-Ching Chao , Yi-Chang Lee , An-Hong Liu
IPC分类号： H01L23/02 , H01L21/44
CPC分类号： H01L21/4853 , H01L21/563 , H01L23/13 , H01L23/3114 , H01L23/3128 , H01L23/49811 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/16225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/4824 , H01L2224/48472 , H01L2224/73204 , H01L2224/73215 , H01L2224/85181 , H01L2224/92147 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/01322 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/05599 , H01L2224/0401
摘要： A pillar grid array package (PGA) includes a substrate, a chip disposed on top of the substrate, and a plurality of stud bumps disposed on bottom of the substrate. The stud bumps are formed in an array and each has a flattened top to electrically connect to a printed circuit board, PCB, by an anisotropic conductive paste to achieve a thin package and to avoid substrate warpage problems of a ball grid array (BGA) during high-temperature reflow processes.
摘要翻译：支柱阵列封装（PGA）包括衬底，设置在衬底顶部的芯片和设置在衬底底部的多个柱形凸块。柱形凸起形成为阵列，并且每个具有平坦的顶部，以通过各向异性导电膏电连接到印刷电路板PCB，以实现薄的封装并避免球栅阵列（BGA）的基板翘曲问题高温回流工艺。

5. 发明申请

US20070069750A1 Method for fabricating a plurality of elastic probes in a row 有权
公开(公告)号：US20070069750A1
公开(公告)日：2007-03-29
申请号：US11605443
申请日：2006-11-29
申请人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
发明人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
IPC分类号： G01R31/02 , H01R43/00
CPC分类号： G01R3/00 , G01R1/06716 , G01R1/06744 , G01R1/07342 , H01R13/2414 , H01R43/007 , Y10T29/49147 , Y10T29/49155 , Y10T29/49204 , Y10T29/49222
摘要： A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.

6. 发明授权

US07477065B2 Method for fabricating a plurality of elastic probes in a row 有权
标题翻译：一排制造多个弹性探针的方法
公开(公告)号：US07477065B2
公开(公告)日：2009-01-13
申请号：US11605443
申请日：2006-11-29
申请人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
发明人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
IPC分类号： G01R31/02
CPC分类号： G01R3/00 , G01R1/06716 , G01R1/06744 , G01R1/07342 , H01R13/2414 , H01R43/007 , Y10T29/49147 , Y10T29/49155 , Y10T29/49204 , Y10T29/49222
摘要： A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.
摘要翻译：公开了一排形成多个弹性探针的方法。首先，提供基板，然后在基板上形成成形层，以便平行地提供两个平坦表面。在基板上和形成层上形成光致抗蚀剂层。然后，对光致抗蚀剂层进行图案化以形成与两个平坦表面之间的界面交叉的多个槽，其中在槽中形成有多个弹性探针。在一个实施例中，界面是成形层的边缘斜率，使得每个弹性探针具有至少一个弹性弯曲部分。在芯片探测期间，由于过驱动导致的弹性探针的移动方向垂直于接合焊盘的布置方向，使得弹性探头适用于探测具有高密度和细间距接合焊盘的芯片。

7. 发明申请

US20070069749A1 Method for fabricating a plurality of elastic probes in a row 审中-公开
标题翻译：一排制造多个弹性探针的方法
公开(公告)号：US20070069749A1
公开(公告)日：2007-03-29
申请号：US11605442
申请日：2006-11-29
申请人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
发明人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
IPC分类号： G01R31/02
CPC分类号： G01R3/00 , G01R1/06716 , G01R1/06744 , G01R1/07342 , H01R13/2414 , H01R43/007 , Y10T29/49147 , Y10T29/49155 , Y10T29/49204 , Y10T29/49222
摘要： A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.
摘要翻译：公开了一排形成多个弹性探针的方法。首先，提供基板，然后在基板上形成成形层，以便平行地提供两个平坦表面。在基板上和形成层上形成光致抗蚀剂层。然后，对光致抗蚀剂层进行图案化以形成与两个平坦表面之间的界面交叉的多个槽，其中在槽中形成有多个弹性探针。在一个实施例中，界面是成形层的边缘斜率，使得每个弹性探针具有至少一个弹性弯曲部分。在芯片探测期间，由于过驱动导致的弹性探针的移动方向垂直于接合焊盘的布置方向，使得弹性探头适用于探测具有高密度和细间距接合焊盘的芯片。

8. 发明申请

US20060267607A1 Method for fabricating a plurality of elastic probes in a row 有权
公开(公告)号：US20060267607A1
公开(公告)日：2006-11-30
申请号：US11364330
申请日：2006-03-01
申请人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
发明人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
IPC分类号： G01R31/02
CPC分类号： G01R3/00 , G01R1/06716 , G01R1/06744 , G01R1/07342 , H01R13/2414 , H01R43/007 , Y10T29/49147 , Y10T29/49155 , Y10T29/49204 , Y10T29/49222
摘要： A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.

9. 发明授权

US07696443B2 Electronic device with a warped spring connector 有权
标题翻译：具有翘曲弹簧连接器的电子设备
公开(公告)号：US07696443B2
公开(公告)日：2010-04-13
申请号：US11188860
申请日：2005-07-26
申请人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Yao-Jung Lee
发明人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Yao-Jung Lee
IPC分类号： H01R12/04 , H05K1/11
CPC分类号： H01L24/72 , G01R1/06727 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/3025 , H01L2924/351 , H01R13/2407 , H05K1/0216 , H05K3/4092 , H01L2924/00
摘要： An electronic device comprises a substrate and at least a warped spring connector. The substrate has a signal bonding pad and a ground plane. The warped spring connector is disposed on the substrate and is connected to the bonding pad. The warped spring connector includes at least a ground lead electrically connected to the ground plane, a dielectric layer on the ground lead, and a transmitting lead on the dielectric layer. The transmitting lead is bonded to the bonding pad. The ground lead is isolated from and close to the transmitting lead to solve cross-talk and noise problem. Furthermore, the coefficient of thermal expansion of the transmitting lead is different from that of the dielectric layer or the ground lead such that the warped spring connector has a suspending end suspending away from the substrate.
摘要翻译：电子设备包括基板和至少一个翘曲的弹簧连接器。衬底具有信号焊盘和接地层。翘曲弹簧连接器设置在基板上并连接到接合垫。翘曲弹簧连接器至少包括电连接到接地平面的接地引线，接地引线上的电介质层和介电层上的传输引线。传输引线接合到焊盘。接地线与发射线隔离并靠近发射线，以解决串扰和噪声问题。此外，传输引线的热膨胀系数与电介质层或接地引线的热膨胀系数不同，使得翘曲弹簧连接器具有悬挂远离基板的悬挂端。

10. 发明申请

US20060043538A1 Bump structure of an opto-electronic chip 审中-公开
标题翻译：凹凸结构的光电芯片
公开(公告)号：US20060043538A1
公开(公告)日：2006-03-02
申请号：US11208595
申请日：2005-08-23
申请人： Yi-Chang Lee , An-Hong Liu , Yeong-Ching Chao , Yao-Jung Lee
发明人： Yi-Chang Lee , An-Hong Liu , Yeong-Ching Chao , Yao-Jung Lee
IPC分类号： H01L23/58 , H01L23/02
CPC分类号： H01L27/14636 , H01L24/10 , H01L2224/05001 , H01L2224/05022 , H01L2224/05567 , H01L2224/05572 , H01L2224/05573 , H01L2224/05624 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/00014
摘要： An opto-electronic chip includes a plurality of multi-level bumps thereon, each consisting of multiple plated layers. The opto-electronic chip has a plurality of bonding pads and an photoelectric effecting region on its active surface. Each multi-level bump comprises at least an electroless-plated nickel (Ni) layer and an electroless-plated gold (Au) layer wherein the nickel layers cover the bonding pads and the gold layers are formed on the tops of the nickel layers. Furthermore, the thickness of the nickel layers is larger than that of the gold layers. The UBM processes in conventional bumping processes are not needed so that the contaminations or damages to the photoelectric effecting region of the opto-electronic chip due to UBM can be eliminated.
摘要翻译：光电芯片包括多个多层凸起，每个由多个镀层组成。光电芯片在其有源表面上具有多个接合焊盘和光电效应区域。每个多级凸块包括至少一种无电镀镍（Ni）层和无电镀金（Au）层，其中镍层覆盖接合焊盘，并且金层形成在镍层的顶部上。此外，镍层的厚度大于金层的厚度。常规碰撞过程中的UBM工艺不需要，可以消除由UBM引起的光电芯片光电效应区域的污染或损坏。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式