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1. 发明申请

US20060022317A1 Chip-under-tape package structure and manufacture thereof 审中-公开
标题翻译：芯片下带封装结构及其制造
公开(公告)号：US20060022317A1
公开(公告)日：2006-02-02
申请号：US11180494
申请日：2005-07-13
申请人： An-Hong Liu , Chao Ching , Yao Lee , Yi-Chang Lee , Hsiang-Ming Huang
发明人： An-Hong Liu , Chao Ching , Yao Lee , Yi-Chang Lee , Hsiang-Ming Huang
IPC分类号： H01L21/50 , H01L23/495
CPC分类号： H01L23/3114 , H01L23/13 , H01L24/48 , H01L24/97 , H01L2224/32225 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/73204 , H01L2224/73215 , H01L2924/00014 , H01L2924/01322 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The invention discloses a chip-under-tape package structure including a flexible substrate, a chip, a plurality of connecting members, a plurality of stud bumps, and a potting adhesive. The flexible substrate includes a plurality of inner pads and a plurality of outer pads. The chip is attached to a lower surface of the flexible substrate and has an active surface thereon providing a plurality of bonding pads which each corresponds to one of the inner pads. Each of the connecting members functions electrically connecting one of the bonding pads with the inner pad corresponding to said one bonding pad. Each of the stud bumps is attached to one of the outer pads. The potting adhesive is coated to seal the connecting members. Accordingly, the invention is capable of preventing the outer pads from being contaminated by the potting adhesive and suitable for low-cost package of high frequency memory chip.
摘要翻译：本发明公开了一种包括柔性基板，芯片，多个连接部件，多个螺柱凸块和灌封粘合剂的芯片下带封装结构。柔性基板包括多个内垫和多个外垫。芯片附接到柔性基板的下表面并且在其上具有有源表面，其上提供多个键合焊盘，每个焊盘对应于内部焊盘之一。每个连接构件使一个接合焊盘与相应于所述一个焊盘的内焊盘电连接。每个螺柱凸块连接到外垫之一。涂覆粘合剂以密封连接构件。因此，本发明能够防止外垫被灌封粘合剂污染，并且适用于低成本的高频存储芯片封装。

2. 发明授权

US08264068B2 Multi-chip stack package structure 有权
公开(公告)号：US08264068B2
公开(公告)日：2012-09-11
申请号：US13004960
申请日：2011-01-12
申请人： David Wei Wang , An-Hong Liu , Hsiang-Ming Huang , Jar-Dar Yang , Yi-Chang Lee
发明人： David Wei Wang , An-Hong Liu , Hsiang-Ming Huang , Jar-Dar Yang , Yi-Chang Lee
IPC分类号： H01L29/40
CPC分类号： H01L24/48 , H01L23/13 , H01L23/3121 , H01L23/49816 , H01L23/5389 , H01L24/05 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/13025 , H01L2224/13099 , H01L2224/13109 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/32227 , H01L2224/451 , H01L2224/48227 , H01L2224/48471 , H01L2224/48479 , H01L2224/73204 , H01L2224/73265 , H01L2224/85051 , H01L2224/85186 , H01L2224/85986 , H01L2224/92 , H01L2224/92247 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/078 , H01L2924/14 , H01L2924/15153 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
摘要： A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.

3. 发明授权

US07642639B2 COB type IC package to enhanced bondibility of bumps embedded in substrate and method for fabricating the same 有权
标题翻译： COB型IC封装，以增强嵌入在衬底中的凸起的焊接性及其制造方法
公开(公告)号：US07642639B2
公开(公告)日：2010-01-05
申请号：US11583951
申请日：2006-10-20
申请人： Hsiang-Ming Huang , An-Hong Liu , Yeong-Jyh Lin , Yi-Chang Lee
发明人： Hsiang-Ming Huang , An-Hong Liu , Yeong-Jyh Lin , Yi-Chang Lee
IPC分类号： H01L23/04 , H01L23/48
CPC分类号： H01L23/3135 , H01L23/3128 , H01L23/4951 , H01L23/4952 , H01L23/49572 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/13099 , H01L2224/13144 , H01L2224/16235 , H01L2224/1624 , H01L2224/2919 , H01L2224/32014 , H01L2224/32057 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/81136 , H01L2224/81801 , H01L2224/83192 , H01L2224/83194 , H01L2224/83385 , H01L2224/83856 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15151 , H01L2924/15311 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An IC package to enhance the bondibility of embedded bumps, primarily includes a substrate having a plurality of bump-accommodating holes, a bumped chip, an encapsulant, and a plurality of external terminals. The substrate further has a plurality of inner pads at one ends of the bump-accommodating holes respectively. The inner pads may be meshed or a soldering layer is disposed thereon for improving bump connection. The chip is attached to the substrate with the bumps aligned and embedded in the corresponding bump-accommodating holes. The encapsulant is at least formed on a lower surface of the substrate to encapsulate the meshes or the soldering layer. By the suspended meshes or/and the soldering layer, the bumps can be easily bonded at lower temperatures to simplify the manufacturing process with shorter electrical conductive paths and thinner package profiles without wire sweeping.
摘要翻译：一种用于增强嵌入式凸块的结合性的IC封装，主要包括具有多个凸块容纳孔，凸起芯片，密封剂和多个外部端子的基板。基板还分别在凸块容纳孔的一端具有多个内垫。内部焊盘可以是啮合的，或者在其上设置焊接层以改善凸块连接。芯片被附接到基板上，凸块对准并嵌入在相应的凸起容纳孔中。密封剂至少形成在基底的下表面上以封装网眼或焊接层。通过悬挂的网格或/和焊接层，可以在较低的温度下容易地接合凸块，以简化具有更短导电路径和更薄的封装形状的制造工艺，而无需扫线。

4. 发明申请

US20090236741A1 CONDUCTIVE STRUCTURE OF A CHIP AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：芯片的导电结构及其制造方法
公开(公告)号：US20090236741A1
公开(公告)日：2009-09-24
申请号：US12262682
申请日：2008-10-31
申请人： Hsiang-Ming HUANG , An-Hong Liu , Yi-Chang Lee , Hao-Yin Tsai , Shu-Ching Ho
发明人： Hsiang-Ming HUANG , An-Hong Liu , Yi-Chang Lee , Hao-Yin Tsai , Shu-Ching Ho
IPC分类号： H01L23/488 , H01L21/44
CPC分类号： H01L24/11 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05644 , H01L2224/13099 , H01L2224/16 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00014
摘要： A conductive structure of a chip and a method for manufacturing the conductive structure are provided. An under bump metal (UBM) is formed on the redistribution layer (RDL) by performing an electroless plating process. Subsequently, the solder bump is formed on the under bump metal for electrical connection. Thus, the photomask can be economized and the cost of manufacturing can be reduced.
摘要翻译：提供了芯片的导电结构和制造导电结构的方法。通过进行化学镀处理，在再分布层（RDL）上形成凹凸金属（UBM）。随后，焊料凸块形成在凸块下金属上用于电连接。因此，可以节省光掩模并且可以降低制造成本。

5. 发明授权

US07554197B2 High frequency IC package and method for fabricating the same 有权
标题翻译：高频IC封装及其制造方法
公开(公告)号：US07554197B2
公开(公告)日：2009-06-30
申请号：US11400182
申请日：2006-04-10
申请人： Hsiang-Ming Huang , An-Hong Liu , Yeong-Jyh Lin , Yi-Chang Lee , Wu-Chang Tu , Chun-Hung Lin , Shih Feng Chiu
发明人： Hsiang-Ming Huang , An-Hong Liu , Yeong-Jyh Lin , Yi-Chang Lee , Wu-Chang Tu , Chun-Hung Lin , Shih Feng Chiu
IPC分类号： H01L23/48 , H01L23/28 , H01L23/29
CPC分类号： H01L24/10 , H01L23/13 , H01L23/3114 , H01L23/49816 , H01L24/06 , H01L24/13 , H01L24/48 , H01L24/81 , H01L24/83 , H01L24/90 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/13 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2224/8121 , H01L2224/81815 , H01L2224/83194 , H01L2224/838 , H01L2224/9202 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the substrate in a manner that the bumps are inserted into the bump holes respectively. The conductive fillers are formed in the bump holes to electrically connect the bumps to the circuit layer of the substrate. The high frequency IC package has a shorter electrical path and a thinner package thickness.
摘要翻译：高频IC封装主要包括衬底，凸起芯片和多个导电填料，其中衬底具有从顶表面到底表面穿透的多个凸起孔。芯片的有源表面以分别插入到凸块孔中的方式附接到基板的顶表面。导电填料形成在凸起孔中，以将凸块电连接到基板的电路层。高频IC封装具有更短的电路径和更薄的封装厚度。

6. 发明授权

US07316065B2 Method for fabricating a plurality of elastic probes in a row 有权
标题翻译：一排制造多个弹性探针的方法
公开(公告)号：US07316065B2
公开(公告)日：2008-01-08
申请号：US11364330
申请日：2006-03-01
申请人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
发明人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
IPC分类号： G01R3/00
CPC分类号： G01R3/00 , G01R1/06716 , G01R1/06744 , G01R1/07342 , H01R13/2414 , H01R43/007 , Y10T29/49147 , Y10T29/49155 , Y10T29/49204 , Y10T29/49222
摘要： A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.
摘要翻译：公开了一排形成多个弹性探针的方法。首先，提供基板，然后在基板上形成成形层，以便平行地提供两个平坦表面。在基板上和形成层上形成光致抗蚀剂层。然后，对光致抗蚀剂层进行图案化以形成与两个平坦表面之间的界面交叉的多个槽，其中在槽中形成有多个弹性探针。在一个实施例中，界面是成形层的边缘斜率，使得每个弹性探针具有至少一个弹性弯曲部分。在芯片探测期间，由于过驱动导致的弹性探针的移动方向垂直于接合焊盘的布置方向，使得弹性探头适用于探测具有高密度和细间距接合焊盘的芯片。

7. 发明申请

US20070152689A1 Modular probe card 有权
标题翻译：模块式探针卡
公开(公告)号：US20070152689A1
公开(公告)日：2007-07-05
申请号：US11322408
申请日：2006-01-03
申请人： Yi-Chang Lee , An-Hong Liu , Hsiang-Ming Huang , Yao-Jung Lee , Yeong-Her Wang
发明人： Yi-Chang Lee , An-Hong Liu , Hsiang-Ming Huang , Yao-Jung Lee , Yeong-Her Wang
IPC分类号： G01R31/02
CPC分类号： G01R1/07378
摘要： A modular probe card comprises a printed circuit board, an interposer, and a probe head where the printed circuit board has a plurality of first contact pads, the probe head has a plurality of second contact pads. The interposer is disposed between the printed circuit board and the probe head where the interposer includes a substrate and a plurality of pogo pins. The substrate has a first surface, a second surface, and a plurality of through holes penetrating from the first surface to the second surface. The pogo pins are secured in the through holes of the substrate. Each of the pogo pins has a first contact point, a second contact point, and a spring therebetween, whereby the first contact points are elastically extruded from the first surface to contact the first contact pad, and the second contact points are elastically extruded from the second surface to contact the second contact pad, so as to overcome the poor electrical connections between the printed circuit board and the probe head through the interposer due to poor coplanarity of the first contact pads of the printed circuit board.
摘要翻译：模块化探针卡包括印刷电路板，插入件和探针头，其中印刷电路板具有多个第一接触焊盘，探头具有多个第二接触焊盘。插入器设置在印刷电路板和探针头之间，其中插入器包括基板和多个弹簧销。基板具有从第一表面到第二表面的第一表面，第二表面和多个通孔。弹簧销固定在基板的通孔中。每个弹簧销具有第一接触点，第二接触点和它们之间的弹簧，由此第一接触点从第一表面弹性挤出以接触第一接触垫，并且第二接触点从第二表面接触第二接触焊盘，以便克服印刷电路板和探针头之间通过插入器的不良电连接，因为印刷电路板的第一接触焊盘的共面性差。

8. 发明申请

US20060231941A1 Pillar grid array package 有权
标题翻译：支柱网格阵列包
公开(公告)号：US20060231941A1
公开(公告)日：2006-10-19
申请号：US11228234
申请日：2005-09-19
申请人： Hsiang-Ming Huang , Yeong-Ching Chao , Yi-Chang Lee , An-Hong Liu
发明人： Hsiang-Ming Huang , Yeong-Ching Chao , Yi-Chang Lee , An-Hong Liu
IPC分类号： H01L23/24 , H01L23/52
CPC分类号： H01L21/4853 , H01L21/563 , H01L23/13 , H01L23/3114 , H01L23/3128 , H01L23/49811 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/16225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/4824 , H01L2224/48472 , H01L2224/73204 , H01L2224/73215 , H01L2224/85181 , H01L2224/92147 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/01322 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/05599 , H01L2224/0401
摘要： A pillar grid array package (PGA) includes a substrate, a chip disposed on top of the substrate, and a plurality of stud bumps disposed on bottom of the substrate. The stud bumps are formed in an array and each has a flattened top to electrically connect to a printed circuit board, PCB, by an anisotropic conductive paste to achieve a thin package and to avoid substrate warpage problems of a ball grid array (BGA) during high-temperature reflow processes.
摘要翻译：支柱阵列封装（PGA）包括衬底，设置在衬底顶部的芯片和设置在衬底底部的多个柱形凸块。柱形凸起形成为阵列，并且每个具有平坦的顶部，以通过各向异性导电膏电连接到印刷电路板PCB，以实现薄的封装并避免球栅阵列（BGA）的基板翘曲问题高温回流工艺。

9. 发明申请

US20110291267A1 Semiconductor wafer structure and multi-chip stack structure 审中-公开
标题翻译：半导体晶圆结构和多芯片堆叠结构
公开(公告)号：US20110291267A1
公开(公告)日：2011-12-01
申请号：US12856754
申请日：2010-08-16
申请人： David Wei Wang , An-Hong Liu , Hsiang-Ming Huang , Yi-Chang Lee
发明人： David Wei Wang , An-Hong Liu , Hsiang-Ming Huang , Yi-Chang Lee
IPC分类号： H01L23/498
CPC分类号： H01L23/481 , H01L21/563 , H01L21/76898 , H01L24/03 , H01L24/04 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05655 , H01L2224/05666 , H01L2224/06181 , H01L2224/11462 , H01L2224/11464 , H01L2224/13022 , H01L2224/13025 , H01L2224/13111 , H01L2224/13144 , H01L2224/13155 , H01L2224/1319 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/73204 , H01L2224/81193 , H01L2224/9202 , H01L2224/92125 , H01L2224/94 , H01L2225/06513 , H01L2225/06544 , H01L2924/0002 , H01L2924/01019 , H01L2924/14 , H01L2924/1461 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface. Hence, the reliability of multi-chip stack package structure can be enhanced with the application of these soft metal caps.
摘要翻译：半导体晶片结构包括第一表面和与第一表面相对的第二表面，形成在第一表面上的多个芯片区域，多个通孔形成在多个芯片区域中的每一个中，所述多个芯片区域连接第一表面和第二表面和形成在每个贯通硅孔中的贯通硅通孔（TSV）电极结构。每个贯通硅通孔电极结构包括形成在通孔的内壁上的电介质层，形成在电介质层的内壁上并在其中限定空位的阻挡层，填充到空位中的填充金属层，所述填充金属层的第一端低于形成凹部的第一表面;以及连接到所述填充金属层的第一端并覆盖所述填充金属层的第一端的软金属帽，其中所述软金属帽的一部分形成在所述凹部并且软金属帽从第一表面突出。因此，通过应用这些软金属盖，可以提高多芯片堆叠封装结构的可靠性。

10. 发明申请

US20080124828A1 Fabrication processes of a MEMS alloy probe 审中-公开
标题翻译： MEMS合金探针的制造工艺
公开(公告)号：US20080124828A1
公开(公告)日：2008-05-29
申请号：US11601753
申请日：2006-11-20
申请人： Hsiang-Ming Huang , An-Hong Liu , Shu-Ching Ho , Yi-Chang Lee , Yeong-Jyh Lin
发明人： Hsiang-Ming Huang , An-Hong Liu , Shu-Ching Ho , Yi-Chang Lee , Yeong-Jyh Lin
IPC分类号： H01L21/56
CPC分类号： G01R1/06744 , G01R3/00
摘要： MEMS processes for fabrication of a MEMS alloy probe are revealed. Multiple layers of the MEMS alloy probe are formed on the substrate in sequences as a first surface layer, a first conductive layer, a core layer, a second conductive layer, and a second surface layer where the width of the first conductive layer is smaller than the one of first surface layer so that all the exposed edges of the first surface layer are not covered by the first conductive layer. The second surface layer is extended from the sidewalls of the core layer to the exposed edges of the first surface layer to encapsulate the core layer, the first conductive layer, and the second conductive layer. The MEMS alloy probe fabricated by the MEMS processes can eliminate the issue of oxidation.
摘要翻译：揭示了用于制造MEMS合金探针的MEMS工艺。多层MEMS合金探针以顺序形成在基板上，作为第一表面层，第一导电层，芯层，第二导电层和第二表面层，其中第一导电层的宽度小于第一表面层中的一个，使得第一表面层的所有暴露边缘都不被第一导电层覆盖。第二表面层从芯层的侧壁延伸到第一表面层的暴露边缘，以封装芯层，第一导电层和第二导电层。通过MEMS工艺制造的MEMS合金探针可以消除氧化问题。

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