专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07354277B2 Land grid array (LGA) interposer utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries 有权
公开(公告)号：US07354277B2
公开(公告)日：2008-04-08
申请号：US11865293
申请日：2007-10-01
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

32. 发明申请

US20080023731A1 Three-dimensional cascaded power distribution in a semiconductor device 有权
标题翻译：半导体器件中的三维级联功率分布
公开(公告)号：US20080023731A1
公开(公告)日：2008-01-31
申请号：US11496120
申请日：2006-07-31
申请人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
发明人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
IPC分类号： H01L29/80
CPC分类号： G11C5/063 , G11C5/14 , H01L21/8221 , H01L27/0688 , H03H1/0007
摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.
摘要翻译：具有降低的功率损耗和/或噪声的IC结构包括以基本上垂直的尺寸堆叠的两个或更多个有源半导体区域，每个有源半导体区域包括有源层。 IC结构还包括两个或更多个电压供应平面，每个电压供应平面对应于相应的一个有源层。

33. 发明授权

US06249227B1 RFID integrated in electronic assets 有权
标题翻译： RFID集成在电子资产中
公开(公告)号：US06249227B1
公开(公告)日：2001-06-19
申请号：US09185858
申请日：1998-11-04
申请人： Michael John Brady , Paul W. Coteus , Dah-Weih Duan , Venkata S. R. Kodukula , Paul Andrew Moskowitz , Alejandro Gabriel Schrott , Robert Jacob Von Gutfeld , James Peter Ward
发明人： Michael John Brady , Paul W. Coteus , Dah-Weih Duan , Venkata S. R. Kodukula , Paul Andrew Moskowitz , Alejandro Gabriel Schrott , Robert Jacob Von Gutfeld , James Peter Ward
IPC分类号： G08B1314
CPC分类号： G08B13/14 , G06K19/0723 , G06K19/07749 , G06K19/07758 , G08B13/2417 , G08B13/2431 , G08B13/2445 , G08B13/2462 , G08B15/001 , H05K1/0266 , H05K1/18 , H05K1/181 , H05K2201/10098
摘要： Methods and apparatus applying RFID technology to identify electronic components, devices, and systems to provide functions such as, for example, security of the assets, inventory tracking of the assets, identification of the assets, and short distance communication between the assets are disclosed. RFID transponders are integrated into electronic components, devices and systems at the component level (i.e., circuit chip, circuit board, etc.), the asset level (i.e., box, computer, etc.), or system level (i.e., network system, computer system, etc.).
摘要翻译：公开了应用RFID技术识别电子元件，设备和系统以提供诸如资产安全性，资产库存跟踪，资产识别以及资产之间的短距离通信等功能的方法和设备。 RFID应答器集成到组件级（即电路芯片，电路板等）的电子组件，设备和系统，资产级（即，盒，计算机等）或系统级（即网络系统，计算机系统等）。

34. 发明授权

US5565816A Clock distribution network 失效
标题翻译：时钟分配网络
公开(公告)号：US5565816A
公开(公告)日：1996-10-15
申请号：US516735
申请日：1995-08-18
申请人： Paul W. Coteus
发明人： Paul W. Coteus
IPC分类号： G06F1/10 , H03K5/15 , H03L7/07 , H03K3/00 , H03K5/13 , H03L7/18
CPC分类号： G06F1/10 , H03K5/1506 , H03L7/07
摘要： A clock distribution network for synchronously coupled electronic communication systems that includes a clock distribution device having a phase locked loop for synchronizing the external clock signals provided to each semiconductive device with each other. The clock distribution device distributes a low speed clock to a large number of clocked semiconductor devices where those devices then internally generate high speed clocks in phase with the low speed clock. The low speed clocks are phase shifted with respect to each other to reduce radiated energy. The ratio of internal to external clock speed is also communicated to each chip so that the chips can be programmed to operate with a variety of external clock speeds. The phase shifting of the external clock to different chips is provided so that the chips can still communicate synchronously at the high speed internal clock.
摘要翻译：一种用于同步耦合电子通信系统的时钟分配网络，其包括具有用于使提供给每个半导体装置的外部时钟信号彼此同步的锁相环的时钟分配装置。时钟分配器件将低速时钟分配给大量的时钟半导体器件，在那些器件内部将与低速时钟同相内部生成高速时钟。低速时钟相对于彼此相移以减少辐射能量。内部与外部时钟速度的比率也传达到每个芯片，使得芯片可以被编程为以各种外部时钟速度运行。提供外部时钟到不同芯片的相移，使得芯片仍然可以在高速内部时钟同步地通信。

35. 发明授权

US5537476A Secure viewing of display units by image superposition and wavelength separation 失效
标题翻译：通过图像叠加和波长分离安全观看显示单元
公开(公告)号：US5537476A
公开(公告)日：1996-07-16
申请号：US342514
申请日：1994-11-21
申请人： Paul W. Coteus , Douglas S. Goodman
发明人： Paul W. Coteus , Douglas S. Goodman
IPC分类号： G09C5/00 , H04N13/00 , H04L9/00
CPC分类号： H04N13/0422 , G09C5/00 , H04N13/0431 , H04N13/0434 , H04N13/0443 , H04N13/0459
摘要： Apparatus for masking a displayed image by mixing the image with a secondary image that is electronically generated to be related to the primary image that when combined with the primary image obscures viewing of the primary image. The primary image is generated in the form of a first set of wavelength bands and the secondary image is a second set of related wavelength bands. A filter is provided to absorb the second set of wavelength bands to permit secure viewing of the primary image.
摘要翻译：用于通过将图像与电子产生的与主图像相关的次要图像混合来掩蔽所显示的图像的装置，当与主图像组合时，该图像掩盖了主图像的观看。主图像以第一组波长带的形式产生，次要图像是第二组相关波长带。提供滤波器以吸收第二组波长带以允许主图像的安全观看。

36. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

37. 发明授权

US09077616B2 T-star interconnection network topology 有权
标题翻译： T星互连网络拓扑
公开(公告)号：US09077616B2
公开(公告)日：2015-07-07
申请号：US13569789
申请日：2012-08-08
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
IPC分类号： H04L12/24 , H04L12/715
CPC分类号： H04L41/0663 , H04L41/12 , H04L41/145 , H04L45/04
摘要： According to one embodiment of the present invention, a system for network communication includes an M dimensional grid of node groups, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one and each node comprises a router and intra-group links directly connecting each node in each node group to every other node in the node group. In addition, the system includes inter-group links directly connecting each node in each node group to a node in each neighboring node group in the M dimensional grid.
摘要翻译：根据本发明的一个实施例，一种用于网络通信的系统包括节点组的M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N大于1，并且每个节点包括路由器和组内链路，将每个节点组中的每个节点直接连接到节点组中的每个其他节点。此外，该系统包括将每个节点组中的每个节点直接连接到M维网格中的每个相邻节点组中的节点的组间链路。

38. 发明申请

US20140071778A1 MEMORY DEVICE REFRESH 有权
标题翻译：存储设备刷新
公开(公告)号：US20140071778A1
公开(公告)日：2014-03-13
申请号：US13609655
申请日：2012-09-11
申请人： Paul W. Coteus , Douglas J. Joseph , Kyu-hyoun Kim
发明人： Paul W. Coteus , Douglas J. Joseph , Kyu-hyoun Kim
IPC分类号： G11C11/402
CPC分类号： G11C11/40611 , G06F13/1668 , Y02D10/14
摘要： According to one embodiment of the present invention, a method for refreshing memory includes receiving a synchronization command at a memory device. An internal refresh timer is reset within the memory device based on receiving the synchronization command. An internal refresh trigger is generated within the memory device based on the internal refresh timer reaching a predetermined value. A refresh of a memory array is performed within the memory device based on the internal refresh trigger.
摘要翻译：根据本发明的一个实施例，一种用于刷新存储器的方法包括在存储器件处接收同步命令。基于接收到同步命令，内存刷新定时器在存储器设备内复位。基于内部刷新定时器达到预定值，在存储器件内产生内部刷新触发。基于内部刷新触发，在存储器装置内执行刷新存储器阵列。

39. 发明申请

US20140044006A1 T-STAR INTERCONNECTION NETWORK TOPOLOGY 有权
标题翻译： T-STAR互联网络拓扑
公开(公告)号：US20140044006A1
公开(公告)日：2014-02-13
申请号：US13569789
申请日：2012-08-08
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
IPC分类号： H04L12/28
CPC分类号： H04L41/0663 , H04L41/12 , H04L41/145 , H04L45/04
摘要： According to one embodiment of the present invention, a system for network communication includes an M dimensional grid of node groups, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one and each node comprises a router and intra-group links directly connecting each node in each node group to every other node in the node group. In addition, the system includes inter-group links directly connecting each node in each node group to a node in each neighboring node group in the M dimensional grid.
摘要翻译：根据本发明的一个实施例，一种用于网络通信的系统包括节点组的M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N大于1，并且每个节点包括路由器和组内链路，将每个节点组中的每个节点直接连接到节点组中的每个其他节点。此外，该系统包括将每个节点组中的每个节点直接连接到M维网格中的每个相邻节点组中的节点的组间链路。

40. 发明授权

US08571847B2 Efficiency of static core turn-off in a system-on-a-chip with variation 失效
标题翻译：在具有变化的片上系统中静态磁芯关断的效率
公开(公告)号：US08571847B2
公开(公告)日：2013-10-29
申请号：US12727984
申请日：2010-03-19
申请人： Chen-Yong Cher , Paul W. Coteus , Alan Gara , Eren Kursun , David P. Paulsen , Brian A. Schuelke , John E. Sheets, II , Shurong Tian
发明人： Chen-Yong Cher , Paul W. Coteus , Alan Gara , Eren Kursun , David P. Paulsen , Brian A. Schuelke , John E. Sheets, II , Shurong Tian
IPC分类号： G06G7/75
CPC分类号： G06F1/3203 , G06F1/206 , G06F1/3237 , G06F11/24 , Y02D10/128 , Y02D10/16
摘要： A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.
摘要翻译：一种用于提高多核处理器中的静态核心关断的效率的处理器实现的方法，所述方法包括：通过模拟在多核处理器的设计处进行多核处理器的关断分析其中所述多核处理器的设计阶段的所述多核处理器的关断分析包括对应于第一多核处理器核的第一输出关闭; 在多核处理器的测试阶段对多核处理器进行关断分析，其中多核处理器的测试阶段的多核处理器的关断分析包括对应于第二多核处理器的第二多输出核心处理器核心关闭; 比较第一输出和第二输出以确定第一输出是否指相同的磁芯作为第二输出关闭; 如果第一输出和第二输出均指向相同的核来关闭，则输出对应于第一多核处理器核心的第三输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式