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1. 发明申请

US20140071778A1 MEMORY DEVICE REFRESH 有权
标题翻译：存储设备刷新
公开(公告)号：US20140071778A1
公开(公告)日：2014-03-13
申请号：US13609655
申请日：2012-09-11
申请人： Paul W. Coteus , Douglas J. Joseph , Kyu-hyoun Kim
发明人： Paul W. Coteus , Douglas J. Joseph , Kyu-hyoun Kim
IPC分类号： G11C11/402
CPC分类号： G11C11/40611 , G06F13/1668 , Y02D10/14
摘要： According to one embodiment of the present invention, a method for refreshing memory includes receiving a synchronization command at a memory device. An internal refresh timer is reset within the memory device based on receiving the synchronization command. An internal refresh trigger is generated within the memory device based on the internal refresh timer reaching a predetermined value. A refresh of a memory array is performed within the memory device based on the internal refresh trigger.
摘要翻译：根据本发明的一个实施例，一种用于刷新存储器的方法包括在存储器件处接收同步命令。基于接收到同步命令，内存刷新定时器在存储器设备内复位。基于内部刷新定时器达到预定值，在存储器件内产生内部刷新触发。基于内部刷新触发，在存储器装置内执行刷新存储器阵列。

2. 发明授权

US09053811B2 Memory device refresh 有权
标题翻译：内存设备刷新
公开(公告)号：US09053811B2
公开(公告)日：2015-06-09
申请号：US13609655
申请日：2012-09-11
申请人： Paul W. Coteus , Douglas J. Joseph , Kyu-hyoun Kim
发明人： Paul W. Coteus , Douglas J. Joseph , Kyu-hyoun Kim
IPC分类号： G11C7/00 , G11C11/406
CPC分类号： G11C11/40611 , G06F13/1668 , Y02D10/14
摘要： According to one embodiment of the present invention, a method for refreshing memory includes receiving a synchronization command at a memory device. An internal refresh timer is reset within the memory device based on receiving the synchronization command. An internal refresh trigger is generated within the memory device based on the internal refresh timer reaching a predetermined value. A refresh of a memory array is performed within the memory device based on the internal refresh trigger.
摘要翻译：根据本发明的一个实施例，一种用于刷新存储器的方法包括在存储器件处接收同步命令。基于接收到同步命令，内存刷新定时器在存储器设备内重置。基于内部刷新定时器达到预定值，在存储器件内产生内部刷新触发。基于内部刷新触发，在存储器装置内执行刷新存储器阵列。

3. 发明授权

US08452919B2 Advanced memory device having improved performance, reduced power and increased reliability 有权
标题翻译：先进的存储器件具有改进的性能，降低的功率和增加的可靠性
公开(公告)号：US08452919B2
公开(公告)日：2013-05-28
申请号：US13567357
申请日：2012-08-06
申请人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
发明人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
IPC分类号： G06F13/00
CPC分类号： G11C7/1078 , G06F11/1028 , G11C7/04 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C11/4076 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
摘要翻译：具有改进性能，降低功耗和增加可靠性的高级内存。存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路对错误控制编码电路检测接收到的命令中的错误。另一个存储器件包括可编程序序。另一存储器件包括快速退出自刷新模式。另一种存储装置包括由特征装置控制的自动刷新功能。另一存储器件包括由存储器件的特性控制的自动刷新功能。

4. 发明授权

US08343804B2 Implementing multiple different types of dies for memory stacking 有权
标题翻译：实现多种不同类型的模具进行内存堆叠
公开(公告)号：US08343804B2
公开(公告)日：2013-01-01
申请号：US13364346
申请日：2012-02-02
申请人： Paul W. Coteus , Kyu-hyoun Kim
发明人： Paul W. Coteus , Kyu-hyoun Kim
IPC分类号： H01L21/00
CPC分类号： H01L24/73 , H01L23/481 , H01L24/06 , H01L24/48 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/06181 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/10253 , H01L2924/1434 , H01L2924/15311 , H01L2224/45099 , H01L2924/00
摘要： A method and structure are provided for implementing multiple different types of dies for memory stacking. A common wafer is provided with a predefined reticle type. The reticle type includes a plurality of arrays, and a plurality of periphery segments. A plurality of through-silicon-vias (TSVs) is placed at boundaries between array and periphery segments. Multiple different types of dies for memory stacking are obtained based upon selected scribing of the dies from the common wafer.
摘要翻译：提供了一种用于实现用于存储器堆叠的多种不同类型的管芯的方法和结构。普通晶片具有预定的掩模版类型。标线型包括多个阵列和多个外围段。多个通硅通孔（TSV）被放置在阵列和外围段之间的边界处。基于从公共晶片选择划线的模具，获得用于存储器堆叠的多种不同类型的管芯。

5. 发明申请

US20110055671A1 ADVANCED MEMORY DEVICE HAVING IMPROVED PERFORMANCE, REDUCED POWER AND INCREASED RELIABILITY 有权
标题翻译：具有改进性能，降低功耗和提高可靠性的高级存储设备
公开(公告)号：US20110055671A1
公开(公告)日：2011-03-03
申请号：US12553400
申请日：2009-09-03
申请人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
发明人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
IPC分类号： G11C7/00 , G11C8/18 , H03M13/09 , G06F11/07 , G06F11/10
CPC分类号： G11C7/1078 , G06F11/1028 , G11C7/04 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C11/4076 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
摘要翻译：具有改进性能，降低功耗和增加可靠性的高级内存。存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路对错误控制编码电路检测接收到的命令中的错误。另一个存储器件包括可编程序序。另一存储器件包括快速退出自刷新模式。另一种存储装置包括由特征装置控制的自动刷新功能。另一存储器件包括由存储器件的特性控制的自动刷新功能。

6. 发明申请

US20100138684A1 MEMORY SYSTEM WITH DYNAMIC SUPPLY VOLTAGE SCALING 审中-公开
标题翻译：具有动态电压范围的存储器系统
公开(公告)号：US20100138684A1
公开(公告)日：2010-06-03
申请号：US12326126
申请日：2008-12-02
申请人： Kyu-hyoun Kim , Paul W. Coteus , Alan Gara , Vipin Patel , Kenneth L. Wright
发明人： Kyu-hyoun Kim , Paul W. Coteus , Alan Gara , Vipin Patel , Kenneth L. Wright
IPC分类号： G06F1/04 , G06F1/08
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： A memory controller, memory device, and method for dynamic supply voltage scaling in a memory system are provided. The method includes receiving a request for a supply voltage change at the memory controller in the memory system, the supply voltage powering the memory device. The method further includes waiting for any current access of the memory device to complete, and disabling a clock between the memory controller and the memory device. The method also includes changing the supply voltage responsive to the request, and enabling the clock.
摘要翻译：提供了一种存储器控制器，存储器件和用于存储器系统中的动态电源电压缩放的方法。该方法包括在存储器系统中的存储器控制器处接收对电源电压变化的请求，为存储器件提供电源电压。该方法还包括等待存储器设备的任何当前访问以完成存储器控制器和存储器设备之间的时钟的禁用。该方法还包括响应于该请求改变电源电压，并启用时钟。

7. 发明申请

US20090201064A1 Phase Interpolator System and Associated Methods 有权
标题翻译：相位插值系统及相关方法
公开(公告)号：US20090201064A1
公开(公告)日：2009-08-13
申请号：US12028973
申请日：2008-02-11
申请人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps , Frank D. Ferrsiolo
发明人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps , Frank D. Ferrsiolo
IPC分类号： H03K3/00
CPC分类号： H03K5/15026 , H03B27/00 , H03H7/21 , H03H11/22 , H03K5/13 , H03K2005/00052 , H03K2005/00065 , H03K2005/00293
摘要： A phase interpolator system is disclosed that may include a clock to provide a clock signal, and a control section in communication with the clock to regulate the strength of the clock signal. The system may also include a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from the control section.
摘要翻译：公开了可以包括提供时钟信号的时钟以及与时钟通信以调节时钟信号的强度的控制部分的相位内插器系统。该系统还可以包括发电机电路，以根据从控制部分接收的时钟信号的强度来产生替代时钟信号。

8. 发明申请

US20090161475A1 SYSTEM FOR PROVIDING READ CLOCK SHARING BETWEEN MEMORY DEVICES 失效
标题翻译：用于在存储器件之间提供读取时钟共享的系统
公开(公告)号：US20090161475A1
公开(公告)日：2009-06-25
申请号：US11959711
申请日：2007-12-19
申请人： Kyu-hyoun Kim , Paul W. Coteus
发明人： Kyu-hyoun Kim , Paul W. Coteus
IPC分类号： G11C8/18
CPC分类号： G11C5/04 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C7/225 , H03L7/07 , H03L7/0812
摘要： A system for providing read clock sharing between memory devices. The system includes a memory device having an external clock receiver, a read clock receiver, and a phase comparator. The phase comparator synchronizes an internal read clock generated at the memory device. The phase comparator additionally synchronizes one of an external clock received by the external clock receiver and an external read clock received by the read clock receiver. The results of the synchronizing are utilized to refresh the internal read clock. The memory device also includes a mechanism, a read clock driver and a mode register fit. The mechanism is utilized to select between the external clock and the external read clock as input to the phase comparator. The read clock driver outputs the internal read clock generated at the memory device to a read clock output pin. The mode register bit controls the selection of the mechanism, the enabling and disabling of the read clock receiver and the enabling and disabling of the read clock driver.
摘要翻译：一种用于在存储器件之间提供读时钟共享的系统。该系统包括具有外部时钟接收器，读取时钟接收器和相位比较器的存储器件。相位比较器同步存储器件产生的内部读时钟。相位比较器还将由外部时钟接收器接收到的外部时钟和由读取时钟接收器接收到的外部读取时钟之一进行同步。利用同步的结果刷新内部读时钟。存储器件还包括机构，读时钟驱动器和模式寄存器配合。该机制用于在外部时钟和外部读取时钟之间选择作为相位比较器的输入。读时钟驱动器将存储器件产生的内部读时钟输出到读时钟输出引脚。模式寄存器位控制机制的选择，读时钟接收器的使能和禁止以及读时钟驱动器的使能和禁止。

9. 发明申请

US20090049365A1 SYSTEM AND METHOD FOR PROVIDING ERROR CORRECTION AND DETECTION IN A MEMORY SYSTEM 有权
标题翻译：用于在存储器系统中提供错误校正和检测的系统和方法
公开(公告)号：US20090049365A1
公开(公告)日：2009-02-19
申请号：US11837785
申请日：2007-08-13
申请人： Kyu-hyoun Kim , Paul W. Coteus , Luis A. Lastras-Montano
发明人： Kyu-hyoun Kim , Paul W. Coteus , Luis A. Lastras-Montano
IPC分类号： G11C29/00 , G06F11/16
CPC分类号： G06F11/1012 , G11C2029/0411
摘要： A system and method for providing error correction and detection in a memory system. The memory system includes a plurality of memory devices, and error detection and correction logic. The error detection and correction logic includes instructions for generating an error correction code (ECC) word that includes bits from two more of the memory devices and from different memory device transfers.
摘要翻译：一种用于在存储器系统中提供纠错和检测的系统和方法。存储器系统包括多个存储器件，以及错误检测和校正逻辑。错误检测和校正逻辑包括用于生成包括来自两个以上存储器设备的位和来自不同存储器件传输的位的纠错码（ECC）字的指令。

10. 发明授权

US08909878B2 Implementing timing alignment and synchronized memory activities of multiple memory devices accessed in parallel 有权
标题翻译：实现并行访问的多个存储器设备的时序校准和同步存储器活动
公开(公告)号：US08909878B2
公开(公告)日：2014-12-09
申请号：US13494280
申请日：2012-06-12
申请人： Paul W. Coteus , Kyu-hyoun Kim
发明人： Paul W. Coteus , Kyu-hyoun Kim
IPC分类号： G06F12/00
CPC分类号： G11C29/26 , G06F13/1684 , G06F13/1689 , G11C29/023 , G11C29/028 , G11C2029/2602
摘要： A method and circuit for implementing synchronized memory activities of multiple memory devices being accessed in parallel, and a design structure on which the subject circuit resides are provided. Each memory circuit generates an internal status signal for predefined internal memory activities and provides an output signal coupled to the multiple memory devices. Each memory circuit monitors the generated internal status signal and the output signal of at least one of the multiple memory devices, and responsive to the monitored signals generates a control signal for adjusting operation of its memory activities to synchronize memory activities of the memory devices.
摘要翻译：一种用于实现并行访问的多个存储器件的同步存储器活动的方法和电路，以及设置有被摄体电路的设计结构。每个存储器电路产生用于预定义的内部存储器活动的内部状态信号，并提供耦合到多个存储器件的输出信号。每个存储器电路监视生成的内部状态信号和多个存储器件中的至少一个的输出信号，并且响应于所监视的信号产生用于调整其存储器活动的操作以控制存储器件的存储器活动的控制信号。

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