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21. 发明授权

US5835047A Folding A/D converter 失效
标题翻译：折叠A / D转换器
公开(公告)号：US5835047A
公开(公告)日：1998-11-10
申请号：US704198
申请日：1996-08-28
申请人： Pieter Vorenkamp , Rudy J. Van De Plassche
发明人： Pieter Vorenkamp , Rudy J. Van De Plassche
IPC分类号： H03M1/14 , H03F3/45 , H03M1/20 , H03M1/36
CPC分类号： H03M1/203 , H03M1/141
摘要： In a folding A/D converter, a comparison part CPM provides a plurality of comparison signals Sc1 . . . Sc9 in response to an input signal Si. The transients in the comparison signals Sc1 . . . Sc9 are mutually shifted and substantially overlap. Because of the overlap, only a relatively small input signal variation is needed to pass all the transients. A limiting part LIM effectively selects portions of the transients. A combining part CBM effectively multiplexes these selected portions into a folding signal Sf. The selection by the limiting part LIM prevents distortion of the folding signal Sf, despite the overlap.
摘要翻译：在折叠A / D转换器中，比较部分CPM提供多个比较信号Sc1。。。 Sc9响应于输入信号Si。比较信号Sc1中的瞬变。。。 Sc9相互偏移并且基本上重叠。由于重叠，只需要相对较小的输入信号变化来传递所有瞬变。限制部分LIM有效地选择部分瞬变。组合部分CBM将这些选择的部分有效地多路复用成折叠信号Sf。限制部分LIM的选择防止折叠信号Sf的失真，尽管重叠。

22. 发明授权

US5252825A Absolute encoder using interpolation to obtain high resolution 失效
标题翻译：绝对编码器采用插补获得高分辨率
公开(公告)号：US5252825A
公开(公告)日：1993-10-12
申请号：US728269
申请日：1991-07-11
申请人： Motokatsu Imai , Koh Ohno , Tsuyoshi Matsumoto
发明人： Motokatsu Imai , Koh Ohno , Tsuyoshi Matsumoto
IPC分类号： G01D5/249 , H03M1/14 , H03M1/26 , H03M1/30 , G01D5/34
CPC分类号： H03M1/143 , H03M1/203 , H03M1/26 , H03M1/30 , H03M1/303
摘要： An absolute encoder device comprises a code plate having a 1-track type absolute pattern whose minimum reading unit length is .lambda., a first incremental pattern with a pitch .lambda., and a second incremental pattern with pitch 2.sup.-n .lambda.. The device also comprises a detector section, which is movable relative to the code plate, which includes a detector detecting the absolute pattern and obtaining an absolute pattern signal, a detector detecting a first incremental pattern and obtaining a first incremental signal, and a detector detecting a second incremental pattern and obtaining a second incremental pattern signal. A shorter cyclic incremental signal is generated from the first incremental signal by interpolating and the shorter cyclic signal is synchronized with the second incremental signal. The absolute pattern signal, the second incremental signal and the synchronized first incremental signal represent the relative positional relationship between the code plate and the detector section.
摘要翻译：绝对编码器装置包括具有最小读取单位长度为λ的1-轨道型绝对图案的代码板，具有间距λ的第一增量图案和具有间距2-nλ的第二增量图案。该装置还包括可相对于码板移动的检测器部分，其包括检测绝对图案并获得绝对图案信号的检测器，检测第一增量图案并获得第一增量信号的检测器，以及检测器检测第二增量模式并获得第二增量模式信号。通过内插从第一增量信号产生较短的循环增量信号，并且较短的循环信号与第二增量信号同步。绝对模式信号，第二增量信号和同步的第一增量信号表示代码板和检测器部分之间的相对位置关系。

23. 发明授权

US4766376A Magnetic position detector for detecting an absolute position of a movable member 失效
标题翻译：磁性位置检测器，用于检测可动件的绝对位置
公开(公告)号：US4766376A
公开(公告)日：1988-08-23
申请号：US896255
申请日：1986-08-14
申请人： Tadashi Takahashi , Kunio Miyashita , Syouichi Kawamata
发明人： Tadashi Takahashi , Kunio Miyashita , Syouichi Kawamata
IPC分类号： G01D5/14 , G01D5/245 , G01D5/249 , H03M1/00 , G01B7/30
CPC分类号： G01D5/145 , G01D5/2497 , H03M1/203 , H03M1/143 , H03M1/26 , H03M1/285
摘要： A magnetic recording medium is provided on a rotary drum and is divided into a plurality of magnetic tracks. On each track is recorded a magnetic signal of a combination of a magnetization portion which consists of two consecutive unit magnets (pitch .lambda.) and a no-magnetization portion having the same length (2.lambda.) that are alternatingly arranged over the whole periphery of the track. First magnetoresistive elements in the magnetic sensor are arranged in pairs so as to be opposed to the magnetic tracks maintaining a distance of .lambda./2. Second magnetoresistive elements opposed to the magnetic track that correponds to the lowest-order bit of position detecting signals, are arranged in a number of ##EQU1## for the first magnetoresistive element maintaining a distance of ##EQU2## wherein SM.sub.L denotes the length of the magnetic signal of the magnetic track, m denotes the number of the increased bits (0
摘要翻译：磁记录介质设置在旋转磁鼓上并被分成多个磁迹。在每个轨道上记录由两个连续的单位磁体（间距λ）组成的磁化部分和具有相同长度（2λ）的非磁化部分的组合的磁信号，所述非磁化部分交替布置在整个周边跟踪。磁传感器中的第一磁阻元件成对配置成与保持λ/ 2的距离的磁道相对。与磁迹相对的第二磁阻元件，其对应于位置检测信号的最低位，被布置成用于第一磁阻元件的数量“IMAGE”，其中第一磁阻元件保持距离“IMAGE”，其中SML表示磁体的长度磁迹的信号，m表示增加位数（0

24. 发明授权

US4587485A Evaluation arrangement for a digital incremental transmitter 失效
标题翻译：数字增量发射机的评估安排
公开(公告)号：US4587485A
公开(公告)日：1986-05-06
申请号：US519579
申请日：1983-08-02
申请人： Wolfgang Papiernik
发明人： Wolfgang Papiernik
IPC分类号： G01D5/245 , G01D5/244 , G08C19/38 , H03M1/30 , G01P3/44 , G01P13/00
CPC分类号： G01D5/24409 , H03M1/203 , H03M1/303
摘要： An evaluation arrangement for a digital incremental transmitter of the type wherein two phase-shifted sinusoidal voltages of the same period are produced generates a periodic triangular voltage signal which is subsequently converted to digital values. The digital values are produced in response to an interlinking of linear portions of the sinusoidal voltages. The digital values are used to address a read-only memory in which are stored a plurality of absolute values within a period.
摘要翻译：这种类型的数字增量发射机的评估装置，其中产生相同周期的两个相移正弦电压产生周期性的三角形电压信号，随后将其转换为数字值。响应于正弦电压的线性部分的互连而产生数字值。数字值用于寻址在一个周期内存储多个绝对值的只读存储器。

25. 发明授权

US10498347B1 Reference voltage sub-system allowing power up from extended periods of ultra-low power standby mode 有权
公开(公告)号：US10498347B1
公开(公告)日：2019-12-03
申请号：US16519339
申请日：2019-07-23
申请人： Ambiq Micro, Inc.
发明人： Ivan Bogue
IPC分类号： H03M1/00 , H03M1/18 , H03M1/20
CPC分类号： H03M1/007 , H03M1/183 , H03M1/185 , H03M1/203 , H03M1/204
摘要： A reference voltage sub-system that allows fast power up after spending extended periods in an ultra-low power standby mode. The reference voltage sub-system includes a reference voltage buffer, a reference voltage keeper, an active calibration facility for selectively adjusting the reference voltage keeper output to match the reference voltage buffer output, and a selection means for selecting between the reference voltage buffer output and the reference voltage keeper output.

26. 发明申请

US20190052825A1 IMAGE SENSOR, ELECTRONIC APPARATUS, COMPARATOR, AND DRIVE METHOD 审中-公开
公开(公告)号：US20190052825A1
公开(公告)日：2019-02-14
申请号：US16162919
申请日：2018-10-17
申请人： Sony Corporation
发明人： Yoshiaki Inada
IPC分类号： H04N5/378 , H04N5/3745 , H04N5/374 , H04N5/363 , H03M1/20 , H03M1/08 , H03M1/56 , H03M1/12 , H04N5/369
CPC分类号： H04N5/378 , H03M1/08 , H03M1/123 , H03M1/203 , H03M1/56 , H04N5/363 , H04N5/3698 , H04N5/374 , H04N5/37455
摘要： The present technology relates to an image sensor, an electronic apparatus, a comparator, and a drive method which enable achievement of a noise reduction while maintaining high speed of AD conversion. An ADC for performing AD conversion for an electrical signal output from a pixel includes a comparator that compares the electrical signal and a reference signal, a level of which is changed and a counter that counts time necessary for a change of the reference signal to a coincidence of the electrical signal and the reference signal on the basis of output signals from the comparator. The comparator includes a differential amplifier that outputs a comparison result signal indicating a comparison result obtained by comparing the electrical signal and the reference signal and a plurality of output amplifiers that outputs signals obtained by amplifying the comparison result signal output from the differential amplifier as the output signals at different timings. The present technology can be applied to, for example, an ADC that performs AD conversion for an electrical signal output from a pixel.

27. 发明授权

US08253616B2 Analog-to-digital conversion in pixel arrays using a ramp signal having a single cycle 有权
标题翻译：使用具有单个周期的斜坡信号的像素阵列中的模数转换
公开(公告)号：US08253616B2
公开(公告)日：2012-08-28
申请号：US12981911
申请日：2010-12-30
申请人： Jan Bogaerts
发明人： Jan Bogaerts
IPC分类号： H03M1/56
CPC分类号： H04N5/3575 , H03M1/1019 , H03M1/123 , H03M1/1295 , H03M1/203 , H03M1/56
摘要： An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC receives a first analog signal level, a second analog signal level and a ramp signal. A counter is operable to count in a single direction. A control stage is arranged to enable the counter based on a comparison of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.
摘要翻译：模数转换器（ADC）产生等于两个模拟信号值之差的输出数字值。 ADC接收第一模拟信号电平，第二模拟信号电平和斜坡信号。计数器可操作以在单个方向上计数。控制级被布置成基于斜坡信号与第一模拟信号和第二模拟信号的比较来使得计数器能够使能。计数器在启用期间累积的数字值形成输出。 ADC可以在斜坡信号的单个周期内执行转换。该计数器可以加载起始数字值，表示在先前曝光期间累积的曝光量。描述了减少转换时间的技术。

28. 发明申请

US20110095929A1 ANALOG-TO-DIGITAL CONVERSION IN PIXEL ARRAYS 有权
标题翻译：像素阵列中的模拟数字转换
公开(公告)号：US20110095929A1
公开(公告)日：2011-04-28
申请号：US12982027
申请日：2010-12-30
申请人： Jan BOGAERTS
发明人： Jan BOGAERTS
IPC分类号： H03M1/56
CPC分类号： H04N5/3575 , H03M1/1019 , H03M1/123 , H03M1/1295 , H03M1/203 , H03M1/56
摘要： An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.
摘要翻译：模数转换器（ADC）产生等于两个模拟信号值之差的输出数字值。 ADC 30接收第一模拟信号电平，第二模拟信号电平和斜坡信号。计数器32可操作以在单个方向上计数。控制级被布置为使得计数器32能够基于斜坡信号与第一模拟信号和第二模拟信号的比较19。计数器在启用期间累积的数字值形成输出。 ADC可以在斜坡信号的单个周期内执行转换。计数器32可以加载代表在先前曝光期间累积的曝光量的开始数字值。描述了减少转换时间的技术。

29. 发明申请

US20110032137A1 HIGH-SPEED ANALOG-DIGITAL CONVERTER HAVING A SIGNAL FOLDING STRUCTURE IMPROVED BY REDUCING THE NUMBER OF ELEMENTARY CELLS 有权
标题翻译：具有通过减少细胞数量改善的信号折叠结构的高速模拟数字转换器
公开(公告)号：US20110032137A1
公开(公告)日：2011-02-10
申请号：US12936312
申请日：2009-03-26
申请人： Sandrine Bruel , Francois Bore
发明人： Sandrine Bruel , Francois Bore
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/0682 , H03M1/203
摘要： The invention relates to high-resolution analog-digital converters using so-called folding differential amplifier structures composed of differential circuits (crossed differential pairs) and of loads (cascode transistors). The folding structure according to the invention comprises, in the case where it is desired to produce four curves folded at two periods in the useful range of voltages to be converted, four folding blocks (one per curve). The first comprises 7 differential circuits and eight loads, the end loads not being linked to the output of the block. The other blocks comprise 6 differential circuits and eight loads, the last load of each block not being linked to the output of this block. Gains are achieved in terms of bulk, consumption and operating speed, with respect to existing structures.
摘要翻译：本发明涉及使用由差分电路（交叉差分对）和负载（共源共栅晶体管）组成的所谓的折叠差分放大器结构的高分辨率模数转换器。根据本发明的折叠结构包括在希望产生在要转换的电压的有用范围内的两个周期折叠的四个曲线的情况下，四个折叠块（每个曲线一个）。第一个包括7个差分电路和8个负载，终端负载不连接到块的输出。其他块包括6个差分电路和8个负载，每个块的最后一个负载不链接到该块的输出。在现有结构方面，在批量，消费和运行速度方面实现了收益。

30. 发明授权

US6016113A System for enhancing the accuracy of analog-digital-analog conversions 失效
标题翻译：提高模数转换精度的系统
公开(公告)号：US6016113A
公开(公告)日：2000-01-18
申请号：US882826
申请日：1997-06-26
申请人： Yehuda Binder
发明人： Yehuda Binder
IPC分类号： H03M1/20 , H03M1/66
CPC分类号： H03M1/207 , H03M1/201 , H03M1/203 , H03M1/66
摘要： An apparatus for and method of enhancing the accuracy of analog-digital-analog conversions achieves improved accuracy by generating a dither signal which is combined with an input analog signal before the analog input signal is converted to digital form. The combined input analog/dither signal is then converted to digital. The digital signal is then processed or delayed in accordance with the desired function to be performed by the circuit. After digital processing, the digital values are converted back into analog form and the dither signal subsequently removed from the output signal. In addition, an apparatus for and method of enhancing the accuracy of analog-digital-analog conversions that does not utilize an explicit dither signal, utilizes linear interpolation techniques to achieve the effect of a pseudo dither signal. Similarly, time multiplexing techniques are also used to achieve the same effect. The principles of the present invention are applicable in systems that generate analog signals using consecutive digital samples. The resultant output signals from such systems exhibit improved accuracy, lower distortion and higher resolution. The present invention can also be utilized to maintain the original output resolution while requiring fewer bits to represent the digital samples.
摘要翻译：用于提高模拟数字 - 模拟转换精度的装置和方法通过在将模拟输入信号转换为数字形式之前产生与输入模拟信号组合的抖动信号来实现提高的精度。然后将组合的输入模拟/抖动信号转换为数字信号。然后根据要由电路执行的期望功能对数字信号进行处理或延迟。在数字处理之后，数字值被转换成模拟形式，并且随后从输出信号中去除抖动信号。此外，用于提高不利用显式抖动信号的模数转换的精度的装置和方法利用线性插值技术来实现伪抖动信号的效果。类似地，时间复用技术也被用于实现相同的效果。本发明的原理适用于使用连续的数字采样产生模拟信号的系统。从这些系统得到的输出信号表现出提高的精度，更低的失真和更高的分辨率。本发明还可以用于维持原始输出分辨率，同时需要较少的比特来表示数字样本。

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