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1. 发明申请

US20160112665A1 IMAGE SENSOR 审中-公开
标题翻译：图像传感器
公开(公告)号：US20160112665A1
公开(公告)日：2016-04-21
申请号：US14515505
申请日：2014-10-15
申请人： Guy Meynants , Jan Bogaerts
发明人： Guy Meynants , Jan Bogaerts
IPC分类号： H04N5/374 , H01L27/146
CPC分类号： H01L27/14643 , H01L27/14609 , H04N5/23245 , H04N5/3559 , H04N5/37452
摘要： An image sensor comprises an array of pixels comprising: a pinned photodiode; a first sense node A; a second sense node B; a transfer gate TX connected between the pinned photodiode and the first sense node A; a first reset transistor M3 connected between a voltage reference line Vrst and the second sense node B; a second reset transistor M4 connected between the first sense node A and the second sense node B; and a buffer amplifier M1 having an input connected to the first sense node A. The control logic is arranged to operate the pixels in a low conversion gain mode and in a high conversion gain mode. In each of the conversion gain modes the control logic is arranged to operate one of a first reset control line RS1 and a second reset control line RS2 to continuously switch on one of the first reset transistor M3 and the second reset transistor M4 during a readout period of an operational cycle of the pixels.
摘要翻译：图像传感器包括像素阵列，包括：钉扎光电二极管; 第一感知节点A; 第二感测节点B; 连接在钉扎光电二极管和第一感测节点A之间的传输门TX; 连接在电压基准线Vrst和第二感测节点B之间的第一复位晶体管M3; 连接在第一感测节点A和第二感测节点B之间的第二复位晶体管M4; 以及具有连接到第一感测节点A的输入端的缓冲放大器M1。控制逻辑被配置为以低转换增益模式和高转换增益模式操作像素。在每个转换增益模式中，控制逻辑被布置成操作第一复位控制线RS1和第二复位控制线RS2中的一个，以在读出期间连续地接通第一复位晶体管M3和第二复位晶体管M4中的一个的像素的操作周期。

2. 发明授权

US07880662B2 Analog-to-digital conversion in pixel arrays 有权
标题翻译：像素阵列中的模数转换
公开(公告)号：US07880662B2
公开(公告)日：2011-02-01
申请号：US12388590
申请日：2009-02-19
申请人： Jan Bogaerts
发明人： Jan Bogaerts
IPC分类号： H03M1/56
CPC分类号： H04N5/3575 , H03M1/1019 , H03M1/123 , H03M1/1295 , H03M1/203 , H03M1/56
摘要： An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.
摘要翻译：模数转换器（ADC）产生等于两个模拟信号值之差的输出数字值。 ADC 30接收第一模拟信号电平，第二模拟信号电平和斜坡信号。计数器32可操作以在单个方向上计数。控制级被布置为使得计数器32能够基于斜坡信号与第一模拟信号和第二模拟信号的比较19。计数器在启用期间累积的数字值形成输出。 ADC可以在斜坡信号的单个周期内执行转换。计数器32可以加载代表在先前曝光期间累积的曝光量的开始数字值。描述了减少转换时间的技术。

3. 发明申请

US20110115663A1 Analog-to-digital conversion in pixel array 有权
标题翻译：像素阵列中的模数转换
公开(公告)号：US20110115663A1
公开(公告)日：2011-05-19
申请号：US12696109
申请日：2010-01-29
申请人： Jan Bogaerts
发明人： Jan Bogaerts
IPC分类号： H03M1/34
CPC分类号： H03M1/123 , H03M1/56
摘要： An analog-to-digital converter generates an output digital value equivalent to the difference between two analog signals. The converter forms part of a set of converters. The converter receives a first analog signal and a second analog signal (Vreset, Vsig) and a ramp signal (Vramp). A clock is dedicated to the converter, or a sub-set of converters. A control stage enables a first counter based on a comparison of the ramp signal with the first analog signal and the second analog signal. The converter can be calibrated by at least one reference signal (Vref1, Vref2) which is common to the set of converters. A-to-D conversion can include a first A-to-D conversion stage which determines a signal range, selected from a plurality of signal ranges, and a second A-to-D conversion stage which determines an M-bit digital value equivalent to the difference between the first and second analog signals by comparing the signals with a ramp signal, with the ramp signal having the signal range determined by the first analog-to-digital conversion stage.
摘要翻译：模拟 - 数字转换器产生与两个模拟信号之间的差值相当的输出数字值。转换器构成一组转换器的一部分。转换器接收第一模拟信号和第二模拟信号（Vreset，Vsig）和斜坡信号（Vramp）。一个时钟专用于转换器或一组转换器。基于斜坡信号与第一模拟信号和第二模拟信号的比较，控制级使第一计数器成为可能。转换器可以通过至少一个参考信号（Vref1，Vref2）进行校准，这是一组转换器所共有的。 A到D转换可以包括确定从多个信号范围中选择的信号范围的第一A到D转换级和确定M位数字值等效的第二A到D转换级通过将信号与斜坡信号进行比较来获得第一和第二模拟信号之间的差异，斜坡信号具有由第一模数转换级确定的信号范围。

4. 发明授权

US06690074B1 Radiation resistant semiconductor device structure 有权
标题翻译：防辐射半导体器件结构
公开(公告)号：US06690074B1
公开(公告)日：2004-02-10
申请号：US10233894
申请日：2002-09-03
申请人： Bart Dierickx , Jan Bogaerts
发明人： Bart Dierickx , Jan Bogaerts
IPC分类号： H01L29772
CPC分类号： H01L31/103 , H01L23/585 , H01L27/14603 , H01L29/0646 , H01L31/1136 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device structure is described for reducing radiation induced current flow caused by incident ionizing radiation. The structure comprises a semiconductor substrate; two or more regions of a first conductivity type in the substrate; and a guard ring of a second conductivity type for obstructing radiation induced parasitic current flow between the two or more regions of the first conductivity type. The structure may be used in a pixel, e.g. in a diode or a transistor, for increasing radiation resistance.
摘要翻译：描述了用于减少由入射电离辐射引起的辐射感应电流的半导体器件结构。该结构包括半导体衬底; 衬底中具有第一导电类型的两个或更多个区域; 以及用于阻挡第一导电类型的两个或更多个区域之间的辐射诱发的寄生电流的第二导电类型的保护环。该结构可以用在像素中，例如，在二极管或晶体管中，用于增加辐射电阻。

5. 发明授权

US08446309B2 Analog-to-digital conversion in pixel arrays 有权
标题翻译：像素阵列中的模数转换
公开(公告)号：US08446309B2
公开(公告)日：2013-05-21
申请号：US13038502
申请日：2011-03-02
申请人： Jan Bogaerts
发明人： Jan Bogaerts
IPC分类号： H03M1/56
CPC分类号： H04N5/3575 , G06J1/00 , H03M1/1019 , H03M1/123 , H03M1/202 , H03M1/56 , H04N5/3742 , H04N5/3743 , H04N5/378
摘要： An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.
摘要翻译：模数转换器（ADC）产生等于两个模拟信号值之差的输出数字值。 ADC 30接收第一模拟信号电平，第二模拟信号电平和斜坡信号。计数器32可操作以在单个方向上计数。控制级被布置为使得计数器32能够基于斜坡信号与第一模拟信号和第二模拟信号的比较19。计数器在启用期间累积的数字值形成输出。 ADC可以在斜坡信号的单个周期内执行转换。计数器32可以加载代表在先前曝光期间累积的曝光量的开始数字值。描述了减少转换时间的技术。

6. 发明授权

US08253617B2 Analog-to-digital conversion in pixel arrays 有权
标题翻译：像素阵列中的模数转换
公开(公告)号：US08253617B2
公开(公告)日：2012-08-28
申请号：US12982027
申请日：2010-12-30
申请人： Jan Bogaerts
发明人： Jan Bogaerts
IPC分类号： H03M1/56
CPC分类号： H04N5/3575 , H03M1/1019 , H03M1/123 , H03M1/1295 , H03M1/203 , H03M1/56
摘要： An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC receives a first analog signal level, a second analog signal level and a ramp signal. A counter is operable to count in a single direction. A control stage is arranged to enable the counter based on a comparison of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.
摘要翻译：模数转换器（ADC）产生等于两个模拟信号值之差的输出数字值。 ADC接收第一模拟信号电平，第二模拟信号电平和斜坡信号。计数器可操作以在单个方向上计数。控制级被布置成基于斜坡信号与第一模拟信号和第二模拟信号的比较来使得计数器能够使能。计数器在启用期间累积的数字值形成输出。 ADC可以在斜坡信号的单个周期内执行转换。该计数器可以加载起始数字值，表示在先前曝光期间累积的曝光量。描述了减少转换时间的技术。

7. 发明申请

US20120175499A1 PIXEL ARRAY WITH GLOBAL SHUTTER 有权
标题翻译：像素阵列与全球快门
公开(公告)号：US20120175499A1
公开(公告)日：2012-07-12
申请号：US13344095
申请日：2012-01-05
申请人： Guy Meynants , Jan Bogaerts
发明人： Guy Meynants , Jan Bogaerts
IPC分类号： H01L27/148 , H01L27/144
CPC分类号： H01L27/14612 , H04N5/353 , H04N5/3559 , H04N5/3575 , H04N5/363 , H04N5/37452
摘要： A pixel includes a photo-sensitive element for generating charges in response to incident radiation. A transfer gate is positioned between the photo-sensitive element and a sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node and an output connected to a sample stage operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.
摘要翻译：像素包括用于响应入射辐射产生电荷的光敏元件。传输门位于感光元件和感测节点之间，用于控制向感测节点传输电荷。复位开关连接到感测节点，用于将感测节点复位到预定电压。第一缓冲放大器具有连接到感测节点的输入端和连接到可操作以对感测节点的值进行采样的采样台的输出。第二缓冲放大器具有连接到样品台的输入。控制电路操作复位开关，并使样品台在感光元件暴露于辐射的同时采样感测节点。像素阵列同时暴露于辐射。可以读取第一曝光期间的采样值，同时在第二曝光期间曝光光敏元件。

8. 发明申请

US20090256060A1 PIXEL ARRAY WITH GLOBAL SHUTTER 有权
标题翻译：像素阵列与全球快门
公开(公告)号：US20090256060A1
公开(公告)日：2009-10-15
申请号：US12408975
申请日：2009-03-23
申请人： Guy MEYNANTS , Jan Bogaerts
发明人： Guy MEYNANTS , Jan Bogaerts
IPC分类号： H01L27/146 , H03F3/08
CPC分类号： H01L27/14612 , H04N5/353 , H04N5/3559 , H04N5/3575 , H04N5/363 , H04N5/37452
摘要： A pixel comprises a photo-sensitive element for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the photo-sensitive element and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is being exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.
摘要翻译：像素包括用于响应于入射辐射产生电荷的感光元件和感测节点。传输门位于感光元件和感测节点之间，用于控制电荷传递到感测节点。复位开关连接到感测节点，用于将感测节点复位到预定电压。第一缓冲放大器具有连接到感测节点的输入。样本级连接到第一缓冲放大器的输出，并且可操作以对感测节点的值进行采样。第二缓冲放大器具有连接到样品台的输入。控制电路操作复位开关，并使样品台在感光元件暴露于辐射的同时采样感测节点。像素阵列同时暴露于辐射。可以读取第一曝光期间的采样值，同时在第二曝光期间曝光光敏元件。

9. 发明授权

US08754357B2 Pixel having two cascade-connected sample stages, pixel array, and method of operating same 有权
标题翻译：具有两个级联连接的采样级的像素，像素阵列及其操作方法
公开(公告)号：US08754357B2
公开(公告)日：2014-06-17
申请号：US13344095
申请日：2012-01-05
申请人： Guy Meynants , Jan Bogaerts
发明人： Guy Meynants , Jan Bogaerts
IPC分类号： H01J40/14 , H01L27/00
CPC分类号： H01L27/14612 , H04N5/353 , H04N5/3559 , H04N5/3575 , H04N5/363 , H04N5/37452
摘要： A pixel includes a photo-sensitive element for generating charges in response to incident radiation. A transfer gate is positioned between the photo-sensitive element and a sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node and an output connected to a sample stage operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.
摘要翻译：像素包括用于响应于入射辐射产生电荷的光敏元件。传输门位于感光元件和感测节点之间，用于控制向感测节点传输电荷。复位开关连接到感测节点，用于将感测节点复位到预定电压。第一缓冲放大器具有连接到感测节点的输入端和连接到可操作以对感测节点的值进行采样的采样台的输出。第二缓冲放大器具有连接到样品台的输入。控制电路操作复位开关，并使样品台在感光元件暴露于辐射的同时采样感测节点。像素阵列同时暴露于辐射。可以读取第一曝光期间的采样值，同时在第二曝光期间曝光光敏元件。

10. 发明授权

US08569671B2 Pixel array capable of performing pipelined global shutter operation including a first and second buffer amplifier 有权
标题翻译：能够执行包括第一和第二缓冲放大器的流水线全局快门操作的像素阵列
公开(公告)号：US08569671B2
公开(公告)日：2013-10-29
申请号：US12408975
申请日：2009-03-23
申请人： Guy Meynants , Jan Bogaerts
发明人： Guy Meynants , Jan Bogaerts
IPC分类号： H01L27/00 , H01J40/14
CPC分类号： H01L27/14612 , H04N5/353 , H04N5/3559 , H04N5/3575 , H04N5/363 , H04N5/37452
摘要： A pixel comprises a photo-sensitive element for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the photo-sensitive element and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is being exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.
摘要翻译：像素包括用于响应于入射辐射产生电荷的感光元件和感测节点。传输门位于感光元件和感测节点之间，用于控制电荷传递到感测节点。复位开关连接到感测节点，用于将感测节点复位到预定电压。第一缓冲放大器具有连接到感测节点的输入。样本级连接到第一缓冲放大器的输出，并且可操作以对感测节点的值进行采样。第二缓冲放大器具有连接到样品台的输入。控制电路操作复位开关，并使样品台在感光元件暴露于辐射的同时采样感测节点。像素阵列同时暴露于辐射。可以读取第一曝光期间的采样值，同时在第二曝光期间曝光光敏元件。

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