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1. 发明申请

US20110095929A1 ANALOG-TO-DIGITAL CONVERSION IN PIXEL ARRAYS 有权
标题翻译：像素阵列中的模拟数字转换
公开(公告)号：US20110095929A1
公开(公告)日：2011-04-28
申请号：US12982027
申请日：2010-12-30
申请人： Jan BOGAERTS
发明人： Jan BOGAERTS
IPC分类号： H03M1/56
CPC分类号： H04N5/3575 , H03M1/1019 , H03M1/123 , H03M1/1295 , H03M1/203 , H03M1/56
摘要： An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.
摘要翻译：模数转换器（ADC）产生等于两个模拟信号值之差的输出数字值。 ADC 30接收第一模拟信号电平，第二模拟信号电平和斜坡信号。计数器32可操作以在单个方向上计数。控制级被布置为使得计数器32能够基于斜坡信号与第一模拟信号和第二模拟信号的比较19。计数器在启用期间累积的数字值形成输出。 ADC可以在斜坡信号的单个周期内执行转换。计数器32可以加载代表在先前曝光期间累积的曝光量的开始数字值。描述了减少转换时间的技术。

2. 发明申请

US20110095926A1 ANALOG-TO-DIGITAL CONVERSION IN PIXEL ARRAYS 有权
公开(公告)号：US20110095926A1
公开(公告)日：2011-04-28
申请号：US12981911
申请日：2010-12-30
申请人： Jan BOGAERTS
发明人： Jan BOGAERTS
IPC分类号： H03M1/12
CPC分类号： H04N5/3575 , H03M1/1019 , H03M1/123 , H03M1/1295 , H03M1/203 , H03M1/56
摘要： An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.

3. 发明申请

US20100148037A1 PIXEL ARRAY WITH SHARED READOUT CIRCUITRY 有权
标题翻译：具有共享读取电路的PIXEL阵列
公开(公告)号：US20100148037A1
公开(公告)日：2010-06-17
申请号：US12544755
申请日：2009-08-20
申请人： Jan BOGAERTS , Guy MEYNANTS
发明人： Jan BOGAERTS , Guy MEYNANTS
IPC分类号： H03K17/78 , H03F3/08
CPC分类号： H01L27/14603 , H01L27/14621 , H01L27/14641 , H04N5/347 , H04N5/3651 , H04N5/367 , H04N5/3745
摘要： A pixel array comprises a plurality of photo-sensitive elements arranged in rows and columns and readout circuitry for reading a value of a photo-sensitive element. Shared readout circuitry is provided for a pair of adjacent photo-sensitive elements. Adjacent instances of the shared readout circuitry are staggered with respect to one another. For a layout having shared readout circuitry for a pair of photo-sensitive elements, adjacent instances of the shared readout circuitry are offset by a horizontal distance of one column and a vertical distance of one row of the array. The shared readout circuitry can serve a pair of adjacent photo-sensitive elements in a row or column of the array, or a pair of photo-sensitive elements which are diagonally adjacent in the array. An improved yield and symmetry results from staggering instances of the shared readout circuitry.
摘要翻译：像素阵列包括以行和列排列的多个光敏元件以及用于读取感光元件的值的读出电路。为一对相邻的感光元件提供共享读出电路。共享读出电路的相邻实例相对于彼此交错。对于具有用于一对光敏元件的共享读出电路的布局，共享读出电路的相邻实例被一列的水平距离和阵列的一行的垂直距离偏移。共享读出电路可以在阵列的行或列中的一对相邻的光敏元件或在阵列中对角相邻的一对光敏元件。由共享读出电路的交错实例产生的改善的产量和对称性。

4. 发明申请

US20120193516A1 HIGH DYNAMIC RANGE PIXEL STRUCTURE 有权
标题翻译：高动态范围像素结构
公开(公告)号：US20120193516A1
公开(公告)日：2012-08-02
申请号：US13362082
申请日：2012-01-31
申请人： Jan BOGAERTS
发明人： Jan BOGAERTS
IPC分类号： H01L27/148 , H01L31/102 , G01J1/44
CPC分类号： H01L27/14612 , H01L27/1461 , H04N5/35572 , H04N5/37452
摘要： A pixel structure comprises a photo-sensitive element PPD for generating charges in response to light and a charge conversion element FD. A first transfer gate TX is connected between the photo-sensitive element PPD and the charge conversion element. A charge storage element PG is connected to the photo-sensitive element PPD. The charge storage element PG has a higher charge storage density than the photo-sensitive element PPD. The charge storage element PG is located on the photo-sensitive element PPD side of the first transfer gate TX and is arranged to collect charges generated by the photo-sensitive element PPD during an integration period. The charge storage element can be a photo gate, photodiode or capacitor. Arrangements are provided with, and without, a potential barrier between the photo-sensitive element PPD and the charge storage element PG.
摘要翻译：像素结构包括用于响应光产生电荷的光敏元件PPD和电荷转换元件FD。第一传输门TX连接在感光元件PPD和电荷转换元件之间。电荷存储元件PG连接到感光元件PPD。电荷存储元件PG具有比感光元件PPD更高的电荷存储密度。电荷存储元件PG位于第一传输门TX的感光元件PPD侧，并且被布置成在积分期间收集由感光元件PPD产生的电荷。电荷存储元件可以是光栅，光电二极管或电容器。在感光元件PPD和电荷存储元件PG之间提供并且不具有势垒的布置。

5. 发明申请

US20140203956A1 ANALOG-TO-DIGITAL CONVERSION IN PIXEL ARRAYS 有权
标题翻译：像素阵列中的模拟数字转换
公开(公告)号：US20140203956A1
公开(公告)日：2014-07-24
申请号：US14158818
申请日：2014-01-18
申请人： Guy Meynants , Bram WOLFS , Jan BOGAERTS
发明人： Guy Meynants , Bram WOLFS , Jan BOGAERTS
IPC分类号： H03M1/34
CPC分类号： H03M1/34 , H03M1/123 , H03M1/56 , H04N5/378
摘要： An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N≧2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.
摘要翻译：用于产生与第一模拟信号电平（Vres）和第二模拟信号电平（Vsig）之间的差相当的输出数字值的模拟 - 数字转换器包括用于接收第一模拟信号电平的至少一个输入端和第二模拟信号电平模拟信号电平，用于接收斜坡信号的输入端和用于接收至少一个时钟信号的输入端。一组N个计数器，其中N≥2，被布置成使用相互偏移的N个时钟信号。控制级被布置成基于斜坡信号与第一模拟信号电平（Vres）和第二模拟信号电平（Vsig）的比较来使N个计数器能够使能。输出级被布置为输出数字值，该数字值是在它们被使能的时段期间由N个计数器累积的值的函数。

6. 发明申请

US20090256735A1 ANALOG-TO-DIGITAL CONVERSION IN PIXEL ARRAYS 有权
标题翻译：像素阵列中的模拟数字转换
公开(公告)号：US20090256735A1
公开(公告)日：2009-10-15
申请号：US12388590
申请日：2009-02-19
申请人： Jan BOGAERTS
发明人： Jan BOGAERTS
IPC分类号： H03M1/56
CPC分类号： H04N5/3575 , H03M1/1019 , H03M1/123 , H03M1/1295 , H03M1/203 , H03M1/56
摘要： An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.
摘要翻译：模数转换器（ADC）产生等于两个模拟信号值之差的输出数字值。 ADC 30接收第一模拟信号电平，第二模拟信号电平和斜坡信号。计数器32可操作以在单个方向上计数。控制级被布置为使得计数器32能够基于斜坡信号与第一模拟信号和第二模拟信号的比较19。计数器在启用期间累积的数字值形成输出。 ADC可以在斜坡信号的单个周期内执行转换。计数器32可以加载代表在先前曝光期间累积的曝光量的开始数字值。描述了减少转换时间的技术。

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