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1. 发明申请

US20180175876A1 ANALOG-TO-DIGITAL CONVERTERS 审中-公开
公开(公告)号：US20180175876A1
公开(公告)日：2018-06-21
申请号：US15651694
申请日：2017-07-17
申请人： SK hynix Inc.
发明人： Keunjin CHANG , Joo Won OH , Donghoon SUNG
IPC分类号： H03M1/12
CPC分类号： H03M1/1245 , H03M1/1205 , H03M1/144 , H03M1/204 , H03M1/361 , H03M1/745
摘要： An analog-to-digital converter ADC may be provided. The ADC may include a current driving circuit. The current driving circuit may include an additive current driving circuit and a subtractive current driving circuit configured for adjusting a voltage level of a node. The ADC may include a comparison circuit including a plurality of comparators. Each of the plurality of comparators may be configured to compare a voltage level of the node with a reference voltage.

2. 发明授权

US08723713B2 Signal interpolation device and parallel A/D converting device 失效
标题翻译：信号插值装置和并行A / D转换装置
公开(公告)号：US08723713B2
公开(公告)日：2014-05-13
申请号：US13717410
申请日：2012-12-17
申请人： Junya Matsuno , Tetsuro Itakura
发明人： Junya Matsuno , Tetsuro Itakura
IPC分类号： H03M1/36
CPC分类号： H03H11/22 , H03M1/204 , H03M1/205 , H03M1/36 , H03M1/365
摘要： There is provided a signal interpolation device, including: a first amplifier to generate a first signal representing a difference between an input signal and a first reference voltage; a second amplifier to generate a second signal representing a difference between the input signal and a second reference voltage; a first output amplifier to amplify the first signal to generate a first output signal; a second output amplifier to amplify the second signal to generate a second output signal; a third output amplifier to amplify a sum of a first interpolation signal and the first signal to generate a third output signal, the first interpolation signal representing a voltage generated by dividing a difference between the first reference voltage and the second reference voltage by “2^n”; and a fourth output amplifier to amplify a difference between the second signal and the first interpolation signal to generate a fourth output signal.
摘要翻译：提供了一种信号插值装置，包括：第一放大器，用于产生表示输入信号和第一参考电压之间的差的第一信号; 第二放大器，用于产生表示所述输入信号和第二参考电压之间的差的第二信号; 第一输出放大器，用于放大第一信号以产生第一输出信号; 第二输出放大器，用于放大第二信号以产生第二输出信号; 第三输出放大器，用于放大第一内插信号和第一信号的和以产生第三输出信号，第一内插信号表示通过将第一参考电压和第二参考电压之差除以“2 ^ n“; 以及第四输出放大器，用于放大第二信号和第一内插信号之间的差以产生第四输出信号。

3. 发明申请

US20120286986A1 A/D CONVERSION CIRCUIT 有权
标题翻译： A / D转换电路
公开(公告)号：US20120286986A1
公开(公告)日：2012-11-15
申请号：US13574513
申请日：2011-01-21
申请人： Hidemi Noguchi
发明人： Hidemi Noguchi
IPC分类号： H03M1/12
CPC分类号： H03M1/445 , H03M1/204 , H03M1/44
摘要： Each of cascade-connected one-bit A/D converters includes first and second amplifier circuits receiving first and second input signals, a third amplifier circuit that outputs an interpolation value of outputs of the first and second amplifier circuits, a comparator that outputs a binary signal having value determined by a polarity of an output of the third amplifier circuit, and a selector that selects two of three outputs of the first to third amplifier circuits, based on a value of the comparator. The selector is set such that direct-current transfer characteristics of two outputs of the selector are folded and symmetrical relative to the midpoint of the first and second input signals.
摘要翻译：每个级联连接的一位A / D转换器包括接收第一和第二输入信号的第一和第二放大器电路，输出第一和第二放大器电路的输出的内插值的第三放大器电路，输出二进制信号具有由第三放大器电路的输出的极性确定的值，以及选择器，其基于比较器的值选择第一至第三放大器电路的三个输出中的两个。选择器被设置为使得选择器的两个输出的直流传递特性相对于第一和第二输入信号的中点折叠和对称。

4. 发明申请

US20120044103A1 PARALLEL INTERPOLATION A/D CONVERTER AND DIGITAL EQUALIZER 审中-公开
标题翻译：并行插值A / D转换器和数字均衡器
公开(公告)号：US20120044103A1
公开(公告)日：2012-02-23
申请号：US13287617
申请日：2011-11-02
申请人： Rie Kaihara , Masakazu Shigemori , Youichi Ogura , Junichi Naka , Tsuyoshi Matsushita
发明人： Rie Kaihara , Masakazu Shigemori , Youichi Ogura , Junichi Naka , Tsuyoshi Matsushita
IPC分类号： H03M1/36
CPC分类号： H03M1/204 , H03M1/365
摘要： A parallel interpolation A/D converter includes a reference voltage generation circuit configured to generate (m+1) different reference voltages VR1-VRm+1, where m is a positive integer, and VR1
摘要翻译：并行内插A / D转换器包括：参考电压产生电路，被配置为产生（m + 1）不同的参考电压VR1-VRm + 1，其中m是正整数，VR1

5. 发明申请

US20110215959A1 COMPARATOR AND ANALOG/DIGITAL CONVERTER 有权
标题翻译：比较器和模拟/数字转换器
公开(公告)号：US20110215959A1
公开(公告)日：2011-09-08
申请号：US13127141
申请日：2009-10-28
申请人： Akira Matsuzawa , Masaya Miyahara
发明人： Akira Matsuzawa , Masaya Miyahara
IPC分类号： H03M1/36 , H03K5/26
CPC分类号： H03K5/2481 , H03K3/356139 , H03K5/249 , H03M1/0682 , H03M1/204 , H03M1/365
摘要： To provide a comparator and an A/D converter having the comparator. The comparator includes a differential amplifier circuit section and a differential latch circuit section. A first input voltage signal, a second input voltage signal and a clock signal are inputted to the differential amplifier circuit section. The differential amplifier circuit section operates base on the clock signal to output a first output voltage signal and a second output voltage signal which respectively correspond to the value the input voltage signal and the value of the reference voltage signal and are amplified. The differential latch circuit section operates based on the first and second output voltage signals to keep and output a comparison result between the first input voltage signal and the second input voltage signal.
摘要翻译：提供具有比较器的比较器和A / D转换器。比较器包括差分放大器电路部分和差分锁存电路部分。第一输入电压信号，第二输入电压信号和时钟信号被输入到差分放大器电路部分。差分放大器电路部分基于时钟信号进行工作，以输出分别对应于输入电压信号的值和参考电压信号的值并被放大的第一输出电压信号和第二输出电压信号。差分锁存电路部分基于第一和第二输出电压信号进行工作，以保持并输出第一输入电压信号和第二输入电压信号之间的比较结果。

6. 发明授权

US07767953B2 Voltage generator, analog-to-digital converter, and image sensor system 有权
标题翻译：电压发生器，模数转换器和图像传感器系统
公开(公告)号：US07767953B2
公开(公告)日：2010-08-03
申请号：US12114310
申请日：2008-05-02
申请人： Yuusuke Yamaoka
发明人： Yuusuke Yamaoka
IPC分类号： H01J40/14 , H03M1/78
CPC分类号： H03K4/023 , H03M1/123 , H03M1/204 , H03M1/56 , H03M1/661
摘要： A ladder resistor circuit generates a plurality of different reference voltages. A plurality of switching circuits correspond to a plurality of taps of the ladder resistor circuit. Each of the plurality of switching circuits is connected at one end to a corresponding one of the taps and connected at the other end to an output node, and has a variable on-resistance value. A control circuit selects continuous n (where n is any integer equal to or greater than 2) of the plurality of switching circuits, turns the n switching circuits on, and sets the respective on-resistance values of the n switching circuits.
摘要翻译：梯形电阻电路产生多个不同的参考电压。多个开关电路对应于梯形电阻电路的多个抽头。多个开关电路中的每一个在一端连接到对应的一个抽头并在另一端连接到输出节点，并具有可变的导通电阻值。控制电路选择多个开关电路的连续n（其中n是等于或大于2的整数），使n个开关电路导通，并设置n个开关电路的各自的导通电阻值。

7. 发明申请

US20080030392A1 A/d Converter 有权
标题翻译： A / D转换器
公开(公告)号：US20080030392A1
公开(公告)日：2008-02-07
申请号：US11629402
申请日：2006-04-20
申请人： Junichi Naka , Koji Sushihara
发明人： Junichi Naka , Koji Sushihara
IPC分类号： H03M1/34 , H03M1/12
CPC分类号： H03M1/0604 , H03M1/204 , H03M1/365
摘要： In an A/D converter, each preamp 102 includes a preamp gain adjusting circuit 109. The preamp gain adjusting circuit 109 suppresses the gain of the preamp 102 and restricts a positive-negative output potential difference of the preamp only when the positive-negative output potential difference of the preamp 102 exceeds a reference potential. Accordingly, in the case where the frequency of an input signal to the A/D converter is high, even when the gain of the preamp is increased due to fabrication process variation, temperature variation or supply voltage variation, output strain of the preamp is minimally caused, and the characteristic degradation of the A/D converter can be suppressed.
摘要翻译：在A / D转换器中，每个前置放大器102包括前置放大器增益调整电路109。前置放大器增益调整电路109抑制前置放大器102的增益，仅在前置放大器102的正负输出电位差超过参考电位时才限制前置放大器的正负输出电位差。因此，在A / D转换器的输入信号的频率高的情况下，即使由于制造工艺变化，温度变化或电源电压变化而增大前置放大器的增益，所以前置放大器的输出应变最小导致，并且可以抑制A / D转换器的特性劣化。

8. 发明授权

US07324038B2 Subranging analog to digital converter with multi-phase clock timing 有权
标题翻译：使用多相时钟定时将模数转换器分段
公开(公告)号：US07324038B2
公开(公告)日：2008-01-29
申请号：US10625702
申请日：2003-07-24
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Ruby van de Plassche , Marcel Lugthart
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Ruby van de Plassche , Marcel Lugthart
IPC分类号： H03M1/12
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
摘要翻译： N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

9. 发明授权

US06888483B2 High speed analog to digital converter 失效
标题翻译：高速模数转换器
公开(公告)号：US06888483B2
公开(公告)日：2005-05-03
申请号：US10893999
申请日：2004-07-20
申请人： Jan Mulder
发明人： Jan Mulder
IPC分类号： H03K17/041 , H03M1/06 , H03M1/08 , H03M1/14 , H03M1/20 , H03M1/36 , H03M1/00
CPC分类号： H03M1/0863 , H03K17/04106 , H03M1/146 , H03M1/204 , H03M1/36 , H03M1/365
摘要： An input stage includes a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array amplifiers receives an input signal and a corresponding reference voltage at its inputs, and wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1.
摘要翻译：输入级包括在每个阵列中串联布置的多个自动调零放大器阵列，其中每个自动调零放大器接收前一自动调零放大器的输出，其中每个阵列放大器中的第一自动调零放大器接收输入信号和对应的参考电压其输入，并且其中至少一个自动调零放大器包括接收对应于输出信号的信号的电路，所述电路在时钟相位phi 2 <！ - SIPO - >并且在时钟相位phi1 <1>中基本上拒绝对应于输出信号的信号。

10. 发明申请

US20030218557A1 Analog to digital converter with interpolation of reference ladder 失效
标题翻译：具有参考梯形图插补的模数转换器
公开(公告)号：US20030218557A1
公开(公告)日：2003-11-27
申请号：US10158774
申请日：2002-05-31
发明人： Jan Mulder
IPC分类号： H03M001/34
CPC分类号： H03K17/04106 , H03M1/146 , H03M1/204 , H03M1/365 , H04L25/026 , H04L25/0276
摘要： An N-bit analog to digital converter includes a reference ladder connected to an input voltage at one end, and to ground at another end, an array of differential amplifiers whose differential inputs are connected to taps from the reference ladder, wherein each amplifier has a first differential input connected to the same tap as a neighboring amplifier, and a second differential input shifted by one tap from the neighboring amplifier, and an encoder that converts outputs of the array to an N-bit output.
摘要翻译： N位模数转换器包括连接到一端的输入电压并在另一端接地的参考梯形图，其差分放大器的阵列与差分输入端连接到来自参考梯形图的抽头，其中每个放大器具有连接到与相邻放大器相同的抽头的第一差分输入和从相邻放大器偏移一抽头的第二差分输入，以及将阵列的输出转换为N位输出的编码器。

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