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1. 发明申请

US20110032137A1 HIGH-SPEED ANALOG-DIGITAL CONVERTER HAVING A SIGNAL FOLDING STRUCTURE IMPROVED BY REDUCING THE NUMBER OF ELEMENTARY CELLS 有权
标题翻译：具有通过减少细胞数量改善的信号折叠结构的高速模拟数字转换器
公开(公告)号：US20110032137A1
公开(公告)日：2011-02-10
申请号：US12936312
申请日：2009-03-26
申请人： Sandrine Bruel , Francois Bore
发明人： Sandrine Bruel , Francois Bore
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/0682 , H03M1/203
摘要： The invention relates to high-resolution analog-digital converters using so-called folding differential amplifier structures composed of differential circuits (crossed differential pairs) and of loads (cascode transistors). The folding structure according to the invention comprises, in the case where it is desired to produce four curves folded at two periods in the useful range of voltages to be converted, four folding blocks (one per curve). The first comprises 7 differential circuits and eight loads, the end loads not being linked to the output of the block. The other blocks comprise 6 differential circuits and eight loads, the last load of each block not being linked to the output of this block. Gains are achieved in terms of bulk, consumption and operating speed, with respect to existing structures.
摘要翻译：本发明涉及使用由差分电路（交叉差分对）和负载（共源共栅晶体管）组成的所谓的折叠差分放大器结构的高分辨率模数转换器。根据本发明的折叠结构包括在希望产生在要转换的电压的有用范围内的两个周期折叠的四个曲线的情况下，四个折叠块（每个曲线一个）。第一个包括7个差分电路和8个负载，终端负载不连接到块的输出。其他块包括6个差分电路和8个负载，每个块的最后一个负载不链接到该块的输出。在现有结构方面，在批量，消费和运行速度方面实现了收益。

2. 发明申请

US20080211705A1 Electronic Network Circuit with Dissymmetrical Differential Pairs 有权
标题翻译：具有不对称差分对的电子网络电路
公开(公告)号：US20080211705A1
公开(公告)日：2008-09-04
申请号：US11994183
申请日：2006-06-23
申请人： Francois Bore , Sandrine Bruel , Marc Wingender
发明人： Francois Bore , Sandrine Bruel , Marc Wingender
IPC分类号： H03M1/36
CPC分类号： H03F3/45744 , H03F3/45085 , H03F3/45596 , H03F2203/45032 , H03F2203/45371 , H03M1/0607 , H03M1/141 , H03M1/362
摘要： The invention relates to integrated circuits comprising a set of identical differential pairs of two transistors each (T1, T2; T3, T4) one receiving a variable voltage (Vinp, Vinn) at its base and the other receiving a fixed reference voltage (Vrefp, Vrefn). In order to reduce the dispersion of the offset voltages of said differential pairs, it is provided that the transistor (T2, T4) that receives a fixed reference voltage has an emitter surface at least twice as large as the transistor (T1, T3) that receives a variable voltage at its base. Application to signal folding circuits and to analog-to-digital converters using differential pairs of transistors.
摘要翻译：本发明涉及集成电路，其包括一组相同的差分对的两个晶体管，每个晶体管（T 1，T 2; T 3，T 4）在其基极处接收可变电压（Vinp，Vinn），而另一个接收固定参考电压（Vrefp，Vrefn）。为了减小所述差分对的偏移电压的偏差，提供了接收固定参考电压的晶体管（T 2，T 4）的发射极表面至少是晶体管的两倍（T 1， T 3）在其基地接收可变电压。应用信号折叠电路和使用差分晶体管对的模数转换器。

3. 发明申请

US20090224805A1 ELECTRONIC CIRCUIT WITH COMPENSATION OF INTRINSIC OFFSET OF DIFFERENTIAL PAIRS 失效
标题翻译：电子线路补偿不平衡对位的内部偏移
公开(公告)号：US20090224805A1
公开(公告)日：2009-09-10
申请号：US12097722
申请日：2006-12-12
申请人： Francois Bore , Sandrine Bruel
发明人： Francois Bore , Sandrine Bruel
IPC分类号： H03K5/22
CPC分类号： H03F3/45748 , H03F3/456 , H03F2203/45212 , H03F2203/45352 , H03F2203/45482 , H03F2203/45504 , H03F2203/45512 , H03F2203/45514 , H03M1/445
摘要： The invention relates to analog integrated electronic circuits using differential pairs. The proposal is for a method of automatic correction of offset voltage. The inputs (V1, V2) of the differential circuit are short circuited during a calibration phase distinct from the normal usage phase. A capacitor is charged through the difference of the output currents of the branches of the differential pair in this phase. The voltage at the terminals of the capacitor is compared with at least one threshold. During the normal usage phase following the calibration phase, the result of the comparison is kept in memory. In the normal usage phase, a correction is applied depending on the result kept in memory to a current source of a follower stage upstream of the differential pair.
摘要翻译：本发明涉及使用差分对的模拟集成电子电路。该建议是针对偏移电压进行自动校正的方法。在与正常使用阶段不同的校准阶段，差分电路的输入（V1，V2）短路。在该阶段，通过差分对的分支的输出电流的差异对电容器进行充电。将电容器端子处的电压与至少一个阈值进行比较。在校准阶段之后的正常使用阶段，将比较结果保存在存储器中。在正常使用阶段，根据保存在存储器中的结果对差分对上游的跟随器级的电流源进行校正。

4. 发明授权

US07515085B2 Electronic network circuit with dissymmetrical differential pairs 有权
标题翻译：具有不对称差分对的电子网络电路
公开(公告)号：US07515085B2
公开(公告)日：2009-04-07
申请号：US11994183
申请日：2006-06-23
申请人： Francois Bore , Sandrine Bruel , Marc Wingender
发明人： Francois Bore , Sandrine Bruel , Marc Wingender
IPC分类号： H03M1/36
CPC分类号： H03F3/45744 , H03F3/45085 , H03F3/45596 , H03F2203/45032 , H03F2203/45371 , H03M1/0607 , H03M1/141 , H03M1/362
摘要： The invention relates to integrated circuits comprising a set of identical differential pairs of two transistors each (T1, T2; T3, T4) one receiving a variable voltage (Vinp, Vinn) at its base and the other receiving a fixed reference voltage (Vrefp, Vrefn). In order to reduce the dispersion of the offset voltages of said differential pairs, it is provided that the transistor (T2, T4) that receives a fixed reference voltage has an emitter surface at least twice as large as the transistor (T1, T3) that receives a variable voltage at its base. Application to signal folding circuits and to analog-to-digital converters using differential pairs of transistors.
摘要翻译：本发明涉及集成电路，其包括一组相同的差分对的两个晶体管，每个晶体管（T1，T2; T3，T4）在其基极处接收可变电压（Vinp，Vinn），另一个接收固定参考电压（Vrefp， Vrefn）。为了减小所述差分对的偏移电压的偏差，接收固定参考电压的晶体管（T2，T4）的发射极表面至少是晶体管（T1，T3）的两倍，在其底部接收可变电压。应用信号折叠电路和使用差分晶体管对的模数转换器。

5. 发明授权

US08184032B2 High-speed analog-digital converter having a signal folding structure improved by reducing the number of elementary cells 有权
标题翻译：具有信号折叠结构的高速模拟数字转换器通过减少基本单元的数量而得到改善
公开(公告)号：US08184032B2
公开(公告)日：2012-05-22
申请号：US12936312
申请日：2009-03-26
申请人： Sandrine Bruel , François Bore
发明人： Sandrine Bruel , François Bore
IPC分类号： H03M1/34
CPC分类号： H03M1/002 , H03M1/0682 , H03M1/203
摘要： The invention relates to high-resolution analog-digital converters using so-called folding differential amplifier structures composed of differential circuits (crossed differential pairs) and of loads (cascode transistors). The folding structure according to the invention comprises, in the case where it is desired to produce four curves folded at two periods in the useful range of voltages to be converted, four folding blocks (one per curve). The first comprises 7 differential circuits and eight loads, the end loads not being linked to the output of the block. The other blocks comprise 6 differential circuits and eight loads, the last load of each block not being linked to the output of this block. Gains are achieved in terms of bulk, consumption and operating speed, with respect to existing structures.
摘要翻译：本发明涉及使用由差分电路（交叉差分对）和负载（共源共栅晶体管）组成的所谓的折叠差分放大器结构的高分辨率模数转换器。根据本发明的折叠结构包括在希望产生在要转换的电压的有用范围内的两个周期折叠的四个曲线的情况下，四个折叠块（每个曲线一个）。第一个包括7个差分电路和8个负载，终端负载不连接到块的输出。其他块包括6个差分电路和8个负载，每个块的最后一个负载不链接到该块的输出。在现有结构方面，在批量，消费和运行速度方面实现了收益。

6. 发明授权

US07737774B2 Electronic circuit with compensation of intrinsic offset of differential pairs 失效
标题翻译：电子电路补偿差分对的固有偏移
公开(公告)号：US07737774B2
公开(公告)日：2010-06-15
申请号：US12097722
申请日：2006-12-12
申请人： François Bore , Sandrine Bruel
发明人： François Bore , Sandrine Bruel
IPC分类号： H03F1/02
CPC分类号： H03F3/45748 , H03F3/456 , H03F2203/45212 , H03F2203/45352 , H03F2203/45482 , H03F2203/45504 , H03F2203/45512 , H03F2203/45514 , H03M1/445
摘要： The invention relates to analog integrated electronic circuits using differential pairs. The proposal is for a method of automatic correction of offset voltage. The inputs (V1, V2) of the differential circuit are short circuited during a calibration phase distinct from the normal usage phase. A capacitor is charged through the difference of the output currents of the branches of the differential pair in this phase. The voltage at the terminals of the capacitor is compared with at least one threshold. During the normal usage phase following the calibration phase, the result of the comparison is kept in memory. In the normal usage phase, a correction is applied depending on the result kept in memory to a current source of a follower stage upstream of the differential pair.
摘要翻译：本发明涉及使用差分对的模拟集成电子电路。该建议是针对偏移电压进行自动校正的方法。在与正常使用阶段不同的校准阶段，差分电路的输入（V1，V2）短路。在该阶段，通过差分对的分支的输出电流的差异对电容器进行充电。将电容器端子处的电压与至少一个阈值进行比较。在校准阶段之后的正常使用阶段，将比较结果保存在存储器中。在正常使用阶段，根据保存在存储器中的结果对差分对上游的跟随器级的电流源进行校正。

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