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21. 发明授权

US4423493A Elastic memory with arrangement for reducing phase fluctuations in the output clock pulse 失效
标题翻译：具有减少输出时钟脉冲相位波动的布置的弹性存储器
公开(公告)号：US4423493A
公开(公告)日：1983-12-27
申请号：US390892
申请日：1982-06-22
申请人： Karl H. Annecke
发明人： Karl H. Annecke
IPC分类号： G06F5/06 , H04J3/07 , G11C7/00 , G11C8/00
CPC分类号： H04J3/073 , G06F5/06 , G06F2205/061
摘要： An arrangement for reducing phase fluctuations in the output or reading clock pulse of elastic memories which are produced during the absence and return of the external input clock pulse. According to the invention, the writing and reading clock pulses are replaced immediately upon the absence of the external input clock pulse by a clock pulse generated at the desired frequency fo so that the minimum distance between the written-in memory cell and the read-out memory cell remains in effect even for the time of the operating malfunction and no additional regulating processes are required when the external input clock pulse re-appears.
摘要翻译：用于减少在外部输入时钟脉冲的不存在和返回期间产生的弹性存储器的输出或读取时钟脉冲中的相位波动的装置。根据本发明，在没有外部输入时钟脉冲的情况下，写入和读取时钟脉冲被替换为以期望频率fo产生的时钟脉冲，使得写入存储单元和读出的最小距离当外部输入时钟脉冲重新出现时，即使在运行故障时，存储单元仍然有效，并且不需要额外的调节过程。

22. 发明授权

US10055193B2 Data transfer between clock domains 有权
公开(公告)号：US10055193B2
公开(公告)日：2018-08-21
申请号：US14409985
申请日：2013-06-20
申请人： NORDIC SEMICONDUCTOR ASA
发明人： Per Carsten Skoglund , Asghar Havashki , Arne Wanvik Venas , Asmund Holen , Markus Bakka Hjerto
IPC分类号： G06F1/04 , G06F1/12 , G06F5/06
CPC分类号： G06F5/06 , G06F2205/061 , G06F2205/102
摘要： An arrangement for transferring a data signal (data_a) from a first clock domain (2) to a second clock domain (4) in a digital system. The arrangement has a signal input (6, 7) for receiving an input signal (data_a) from the first clock domain (2), means (6, 7) for storing the input signal (data_a), and means (12, 13) for transferring the input signal (data_a) to the second clock domain (4) following a transition in the clock signal (ck) of the second clock domain (4).

23. 发明申请

US20150205579A1 DETERMINISTIC FIFO BUFFER 有权
标题翻译：确定FIFO缓冲区
公开(公告)号：US20150205579A1
公开(公告)日：2015-07-23
申请号：US14158439
申请日：2014-01-17
申请人： ALTERA CORPORATION
发明人： David W. MENDEL , Dana HOW
IPC分类号： G06F5/14
CPC分类号： G06F5/14 , G06F5/12 , G06F2205/061
摘要： One embodiment relates to a method for determining a latency of a FIFO buffer. A highest-order bit is provided from FIFO write and read counters to input-comparison logic that distinguishes between the highest-order write and read bits having a same logic level and the highest-order write and read bits having different logic levels. The occupancy level, and hence the latency, of the FIFO buffer is determined based on the output of the input-comparison logic. Another embodiment relates to a FIFO buffer having write and read counters that each have a length in bits that is one bit longer than is needed to address the FIFO buffer. Another embodiment relates to a method of tuning a latency of a FIFO buffer. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种用于确定FIFO缓冲器的等待时间的方法。从FIFO写入和读取计数器到输入比较逻辑提供了一个最高位，以区分具有相同逻辑电平的最高位写入位和读取位以及具有不同逻辑电平的最高位写入和读取位。基于输入比较逻辑的输出来确定FIFO缓冲器的占用水平，因此等待时间。另一个实施例涉及一种具有写入和读出计数器的FIFO缓冲器，其每一个具有比寻址FIFO缓冲器所需的位长一位的位长度。另一个实施例涉及一种调整FIFO缓冲器等待时间的方法。还公开了其它实施例和特征。

24. 发明授权

US08327056B1 Processor management using a buffer 有权
标题翻译：处理器管理使用缓冲区
公开(公告)号：US08327056B1
公开(公告)日：2012-12-04
申请号：US13333551
申请日：2011-12-21
申请人： Ting Li Chan , Fredarico E Dutton
发明人： Ting Li Chan , Fredarico E Dutton
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： G06F5/12 , G06F1/3209 , G06F1/3237 , G06F1/3287 , G06F2205/061 , G06F2205/126 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.
摘要翻译：在一个实施例中，一种装置包括缓冲器，多个处理器和处理器控制模块。处理器控制模块至少部分地基于存储在缓冲器中的数据的量来管理多个处理器用于处理来自缓冲器的数据。

25. 发明授权

US08237980B2 Serial interface device and image forming apparatus 失效
标题翻译：串行接口装置和图像形成装置
公开(公告)号：US08237980B2
公开(公告)日：2012-08-07
申请号：US11751796
申请日：2007-05-22
申请人： Tatsuhiko Murata , Masayu Fujiwara , Tomoki Yamamoto , Takeshi Matsuzaki
发明人： Tatsuhiko Murata , Masayu Fujiwara , Tomoki Yamamoto , Takeshi Matsuzaki
IPC分类号： H03M5/08 , H03M5/22 , H03M9/00 , H04N1/00
CPC分类号： H03M9/00 , G06F5/06 , G06F2205/061
摘要： A serial I/F has: a FIFO portion to which m- or n-bit (m
摘要翻译：串行I / F具有：基于PCLK写入m位或n位（m

26. 发明授权

US08135105B2 Circuit for correcting an output clock frequency in a receiving device 有权
标题翻译：用于校正接收装置中的输出时钟频率的电路
公开(公告)号：US08135105B2
公开(公告)日：2012-03-13
申请号：US12214288
申请日：2008-06-17
申请人： Zhibing Liu , Sheng-Chiech Liang
发明人： Zhibing Liu , Sheng-Chiech Liang
IPC分类号： H04L7/00
CPC分类号： H04L7/02 , G06F5/06 , G06F2205/061 , G09G5/008 , H03L7/183 , H04L7/005
摘要： An output clock correction circuit (14) for correcting a frequency of an output clock in a receiving device (13) that receives data (16) and a time stamp component (18) includes an output clock feedback loop (20), a FIFO buffer (22) and a time stamp adjuster (24). The output clock feedback loop (20) adjusts a phase and/or a frequency of the output clock based at least partially on the time stamp component (18). The FIFO buffer (22) temporarily stores the data (16). The time stamp adjuster (24) selectively adjusts the time stamp component (18) based on a status of the FIFO buffer (22). In one embodiment, the status is based at least in part on an actual data level in the FIFO buffer (22). In another embodiment, the FIFO buffer (22) has a target data level range, and the time stamp adjuster (24) adjusts the time stamp component (18) when the actual data level in the FIFO buffer (22) is outside this range. The time stamp adjuster (24) can adjust the time stamp component (18) by an amount that is based on a calculation, or an amount that is determined from a lookup table.
摘要翻译：一种用于校正接收数据（16）和时间戳分量（18）的接收装置（13）中的输出时钟的频率的输出时钟校正电路（14），包括输出时钟反馈回路（20），FIFO缓冲器（22）和时间戳调整器（24）。输出时钟反馈回路（20）至少部分地基于时间戳组件（18）来调整输出时钟的相位和/或频率。 FIFO缓冲器（22）临时存储数据（16）。时间戳调整器（24）基于FIFO缓冲器（22）的状态选择性地调整时间戳分量（18）。在一个实施例中，状态至少部分地基于FIFO缓冲器（22）中的实际数据电平。在另一实施例中，FIFO缓冲器（22）具有目标数据电平范围，并且当FIFO缓冲器（22）中的实际数据电平在该范围之外时，时间戳调整器（24）调整时间戳分量（18）。时间戳调整器（24）可以基于计算的量或从查找表确定的量来调整时间戳组件（18）。

27. 发明授权

US07827377B2 Method for reading out sensor data 有权
标题翻译：读出传感器数据的方法
公开(公告)号：US07827377B2
公开(公告)日：2010-11-02
申请号：US11664379
申请日：2005-08-03
申请人： Christian Ohl , Andreas Fink , Maike Moldenhauer
发明人： Christian Ohl , Andreas Fink , Maike Moldenhauer
IPC分类号： G06F12/00
CPC分类号： G06F5/12 , B60R2021/01068 , G06F5/14 , G06F2205/061
摘要： A method is described for reading out sensor data from an intermediate memory written by at least one sensor to the intermediate memory at a data-transfer rate (Tpas). A sampling rate (Tsg) is selected in such a way as to avoid an overflow of the intermediate memory and all buffered sensor data is read into a control unit memory at the predetermined sampling rate (Tsg), the intermediate memory generating a message (RBE) if no new sensor data is present in the intermediate memory at the time of sampling.
摘要翻译：描述了一种用于以由数据传送速率（Tpas）从中间存储器读出由至少一个传感器写入的中间存储器的传感器数据的方法。选择采样率（Tsg）以避免中间存储器的溢出，并且所有缓冲的传感器数据以预定采样率（Tsg）被读入控制单元存储器，中间存储器产生消息（RBE ）如果在采样时没有新的传感器数据存在于中间存储器中。

28. 发明申请

US20090310729A1 Circuit for correcting an output clock frequency in a receiving device 有权
标题翻译：用于校正接收装置中的输出时钟频率的电路
公开(公告)号：US20090310729A1
公开(公告)日：2009-12-17
申请号：US12214288
申请日：2008-06-17
申请人： Zhibing Liu , Sheng-Chiech Liang
发明人： Zhibing Liu , Sheng-Chiech Liang
IPC分类号： H04L7/00
CPC分类号： H04L7/02 , G06F5/06 , G06F2205/061 , G09G5/008 , H03L7/183 , H04L7/005
摘要： An output clock correction circuit (14) for correcting a frequency of an output clock in a receiving device (13) that receives data (16) and a time stamp component (18) includes an output clock feedback loop (20), a FIFO buffer (22) and a time stamp adjuster (24). The output clock feedback loop (20) adjusts a phase and/or a frequency of the output clock based at least partially on the time stamp component (18). The FIFO buffer (22) temporarily stores the data (16). The time stamp adjuster (24) selectively adjusts the time stamp component (18) based on a status of the FIFO buffer (22). In one embodiment, the status is based at least in part on an actual data level in the FIFO buffer (22). In another embodiment, the FIFO buffer (22) has a target data level range, and the time stamp adjuster (24) adjusts the time stamp component (18) when the actual data level in the FIFO buffer (22) is outside this range. The time stamp adjuster (24) can adjust the time stamp component (18) by an amount that is based on a calculation, or an amount that is determined from a lookup table.
摘要翻译：一种用于校正接收数据（16）和时间戳分量（18）的接收装置（13）中的输出时钟的频率的输出时钟校正电路（14），包括输出时钟反馈回路（20），FIFO缓冲器（22）和时间戳调整器（24）。输出时钟反馈回路（20）至少部分地基于时间戳组件（18）来调整输出时钟的相位和/或频率。 FIFO缓冲器（22）临时存储数据（16）。时间戳调整器（24）基于FIFO缓冲器（22）的状态选择性地调整时间戳分量（18）。在一个实施例中，状态至少部分地基于FIFO缓冲器（22）中的实际数据电平。在另一实施例中，FIFO缓冲器（22）具有目标数据电平范围，并且当FIFO缓冲器（22）中的实际数据电平在该范围之外时，时间戳调整器（24）调整时间戳分量（18）。时间戳调整器（24）可以基于计算的量或从查找表确定的量来调整时间戳组件（18）。

29. 发明授权

US07305059B2 Method and device for the clocked output of asynchronously received digital signals 有权
标题翻译：用于异步接收的数字信号的时钟输出的方法和设备
公开(公告)号：US07305059B2
公开(公告)日：2007-12-04
申请号：US10618378
申请日：2003-07-11
申请人： Stefan Eder , Gunther Fenzl
发明人： Stefan Eder , Gunther Fenzl
IPC分类号： H03D3/24 , H04L1/16 , H04L7/00
CPC分类号： G06F5/14 , G06F2205/061 , H04J3/0632
摘要： A method and device for the uniform output of asynchronously transmitted digital values is provided, including: receiving the digital values in a receiver from a transmission path; outputting the digital values from the receiver on the basis of an output clock for further processing; transmitting the digital values to the transmission path by a transmission device of the receiver, determining the amount of the digital values received by the receiver in relation to the time; adjusting the output clock on the basis of the determined amount in such a way that the digital values are outputted at the frequency with which on time average the receiver receives the digital values; and adjusting a transmission clock of the transmission device to correspond to the output clock of the receiver.
摘要翻译：提供了一种用于均匀输出异步传输数字值的方法和装置，包括：从传输路径接收接收机中的数字值; 基于用于进一步处理的输出时钟从接收器输出数字值; 通过接收机的发送装置将数字值发送到传输路径，确定接收机相对于时间接收的数字值的数量; 基于确定的量调节输出时钟，使得数字值以接收器接收数字值的时间平均的频率输出; 以及调整所述传输设备的传输时钟以对应于所述接收机的输出时钟。

30. 发明授权

US07272675B1 First-in-first-out (FIFO) memory for buffering packet fragments through use of read and write pointers incremented by a unit access and a fraction of the unit access 有权
$First-in-first-out (FIFO) memory for buffering packet fragments through use of read and write pointers incremented by a unit access and a fraction of the unit access$
标题翻译：先进先出（FIFO）存储器，用于通过使用由单位访问增加的读取和写入指针以及单位访问的一部分来缓冲分组片段
公开(公告)号：US07272675B1
公开(公告)日：2007-09-18
申请号：US10841865
申请日：2004-05-06
申请人： Somnath Paul , Sanjay Rekhi
发明人： Somnath Paul , Sanjay Rekhi
IPC分类号： G06F3/00 , G06F5/00 , G06F9/40
CPC分类号： G06F5/10 , G06F5/14 , G06F2205/061 , G06F2205/106 , G06F2205/108
摘要： Disclosed is an apparatus and method used in an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments, comprising a first-in-first-out (FIFO) memory, a read pointer of the FIFO memory, the read pointer to increment by at least one of a unit access per read and a fraction of the unit access per read, and a write pointer of the FIFO memory, the write pointer to increment by at least one of a unit access per write and a fraction of the unit access per write.
摘要翻译：公开了一种在用于调度背对背多信道分组片段的存储转发的接口中使用的装置和方法，包括先进先出（FIFO）存储器，FIFO存储器的读指针，所述读取指针通过每次读取的单位访问和每次读取的单位访问的一小部分以及FIFO存储器的写入指针中的至少一个来增加，所述写入指针通过每次写入的单位访问中的至少一个来增加，以及每次写入单位访问的一小部分。

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