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1. 发明授权

US07379467B1 Scheduling store-forwarding of back-to-back multi-channel packet fragments 有权
标题翻译：调度背对背多通道数据包片段的存储转发
公开(公告)号：US07379467B1
公开(公告)日：2008-05-27
申请号：US10841774
申请日：2004-05-06
申请人： Somnath Paul , Sanjay Rekhi
发明人： Somnath Paul , Sanjay Rekhi
IPC分类号： H04L12/28 , H04L12/56 , H04J3/16
CPC分类号： H04L49/9094 , H04L12/5601 , H04L49/608 , H04L49/90 , H04L49/901 , H04L2012/5652 , H04L2012/5679
摘要： Disclosed is an apparatus and method for an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments. The apparatus may include a data extraction block, a plurality of data assemblers, a scheduler, and an output memory. The scheduler may be configured to operate according to a scheduling policy. The scheduling policy may include a set of priorities to determine an order of scheduling writes to the output memory from a plurality of data assemblers. The scheduling policy may also include selecting one or more of the plurality of data assemblers having a fill level greater than twice an input data path width of an input data bus and having no end-of-packet (EOP) or start-of-packet (SOP) as a first priority, selecting one or more of the plurality of data assemblers having a fill level greater than twice the input data path width of the input data bus, and not covered in the first priority selection, as a second priority, selecting one or more of the plurality of data assemblers having a fill level greater than the input data path width of the input data bus, and not covered in the first and second priority selections, as a third priority, and selecting one or more of the plurality of data assemblers having an end-of-packet (EOP) as a fourth priority.
摘要翻译：公开了一种用于调度背对背多信道分组片段的存储转发的接口的装置和方法。该装置可以包括数据提取块，多个数据组装器，调度器和输出存储器。调度器可以被配置为根据调度策略进行操作。调度策略可以包括一组优先级，以确定从多个数据汇编器调度对输出存储器的写入的顺序。调度策略还可以包括选择多个数据汇编器中的一个或多个具有大于输入数据总线的输入数据路径宽度的两倍的填充水平并且没有分组结束（EOP）或分组开始（SOP）作为第一优先级，选择所述多个数据组合器中的一个或多个具有大于输入数据总线的输入数据路径宽度的两倍的填充水平，并且在第一优先级选择中不被覆盖，作为第二优先级，选择所述多个数据组合器中的一个或多个具有大于所述输入数据总线的输入数据路径宽度的填充水平，并且在第一和第二优先级选择中未被覆盖的第一优先级和第二优先级，并且选择一个或多个具有作为第四优先级的分组结束（EOP）的多个数据组装器。

2. 发明授权

US07272675B1 First-in-first-out (FIFO) memory for buffering packet fragments through use of read and write pointers incremented by a unit access and a fraction of the unit access 有权
$First-in-first-out (FIFO) memory for buffering packet fragments through use of read and write pointers incremented by a unit access and a fraction of the unit access$
标题翻译：先进先出（FIFO）存储器，用于通过使用由单位访问增加的读取和写入指针以及单位访问的一部分来缓冲分组片段
公开(公告)号：US07272675B1
公开(公告)日：2007-09-18
申请号：US10841865
申请日：2004-05-06
申请人： Somnath Paul , Sanjay Rekhi
发明人： Somnath Paul , Sanjay Rekhi
IPC分类号： G06F3/00 , G06F5/00 , G06F9/40
CPC分类号： G06F5/10 , G06F5/14 , G06F2205/061 , G06F2205/106 , G06F2205/108
摘要： Disclosed is an apparatus and method used in an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments, comprising a first-in-first-out (FIFO) memory, a read pointer of the FIFO memory, the read pointer to increment by at least one of a unit access per read and a fraction of the unit access per read, and a write pointer of the FIFO memory, the write pointer to increment by at least one of a unit access per write and a fraction of the unit access per write.
摘要翻译：公开了一种在用于调度背对背多信道分组片段的存储转发的接口中使用的装置和方法，包括先进先出（FIFO）存储器，FIFO存储器的读指针，所述读取指针通过每次读取的单位访问和每次读取的单位访问的一小部分以及FIFO存储器的写入指针中的至少一个来增加，所述写入指针通过每次写入的单位访问中的至少一个来增加，以及每次写入单位访问的一小部分。

3. 发明申请

US20220012563A1 METHODS AND APPARATUS FOR HIGH THROUGHPUT COMPRESSION OF NEURAL NETWORK WEIGHTS 有权
公开(公告)号：US20220012563A1
公开(公告)日：2022-01-13
申请号：US17484226
申请日：2021-09-24
申请人： Alejandro Castro Gonzalez , Praveen Nair , Somnath Paul , Sudheendra Kadri , Palanivel Guruvareddiar , Aaron Gubrud , Vinodh Gopal
发明人： Alejandro Castro Gonzalez , Praveen Nair , Somnath Paul , Sudheendra Kadri , Palanivel Guruvareddiar , Aaron Gubrud , Vinodh Gopal
IPC分类号： G06N3/04
摘要： Methods, apparatus, systems, and articles of manufacture are disclosed for high throughput compression of neural network weights. An example apparatus includes at least one memory, instructions in the apparatus and processor circuitry to execute the instructions to determine sizes of data lanes in a partition of neural network weights, determine a slice size based on a size difference between a first data lane and a second data lane of the data lanes in the partition, the first data lane including first data, the second data lane including second data, the second data of a smaller size than the first data, cut a portion of the first data from the first data lane based on the slice size, and append the portion of the first data to the second data lane.

4. 发明授权

US09337952B2 Embedded resilient buffer 有权
标题翻译：嵌入式弹性缓冲区
公开(公告)号：US09337952B2
公开(公告)日：2016-05-10
申请号：US13867968
申请日：2013-04-22
申请人： Somnath Paul , Sriram R. Vangal
发明人： Somnath Paul , Sriram R. Vangal
IPC分类号： H04L1/00 , H03K19/00 , G06F11/26 , G11C29/00 , G11C29/02 , G06F13/16 , H04L12/70
CPC分类号： G06F11/0787 , G06F5/065 , G06F11/0757 , G06F11/0772 , G06F11/1407 , G06F11/1645 , G06F11/26 , G06F13/1673 , G06F13/1689 , G06F2205/067 , G11C29/003 , G11C29/023 , G11C29/028 , H03K19/00 , H04L1/00 , H04L2012/5681 , Y02D10/14
摘要： Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.
摘要翻译：描述了一种装置，包括：第一顺序单元; 与第一顺序单元并联耦合的第一队列，使得第一队列和第一顺序单元接收第一输入，用于对第一输入进行双倍采样的第一序列; 比较单元，用于接收来自第一顺序单元的输出; 以及由前一周期的写指针控制的第一选择单元，所述第一选择单元接收所述第一队列的每个存储单元的输出，其中所述第一选择单元生成用于由所述第一比较单元进行比较的输出。

5. 发明授权

US07138930B1 Multiple byte data path encoding/decoding device and method 有权
标题翻译：多字节数据路径编码/解码装置及方法
公开(公告)号：US07138930B1
公开(公告)日：2006-11-21
申请号：US10937138
申请日：2004-09-09
申请人： Somnath Paul , Hamid Khodabandehlou
发明人： Somnath Paul , Hamid Khodabandehlou
IPC分类号： H03M7/00
CPC分类号： H03M5/145 , H04L25/14 , H04L25/4906
摘要： Systems and methods for performing encoding and/or decoding can include an input data path that receives multiple input data values having an order (significance) with respect to one another. Each input data value can be applied to multiple compute paths (106-1 to 106-N), each of which can precompute multiple output values based on a different predetermined disparity value. Multiplexers (114-1 to 114-N) can output one precomputed output value according to a disparity value corresponding to a previous input data value in the order.
摘要翻译：用于执行编码和/或解码的系统和方法可以包括输入数据路径，其接收具有相对于彼此的顺序（重要性）的多个输入数据值。每个输入数据值可以应用于多个计算路径（106-1至106-N），每个计算路径可以基于不同的预定差异值预先计算多个输出值。多路复用器（114-1至114-N）可以根据与先前输入数据值相对应的视差值输出一个预计算的输出值。

6. 发明授权

US06925506B1 Architecture for implementing virtual multiqueue fifos 失效
标题翻译：用于实现虚拟多队列fifos的架构
公开(公告)号：US06925506B1
公开(公告)日：2005-08-02
申请号：US09676704
申请日：2000-09-29
申请人： S. Babar Raza , Somnath Paul
发明人： S. Babar Raza , Somnath Paul
IPC分类号： G06F5/06 , G06F12/00 , G06F13/00
CPC分类号： G06F5/065 , G06F2205/066
摘要： A circuit configured to provide a storage device comprising one or more virtual multiqueue FIFOs. The circuit is generally configured to operate at a preferred clock speed of a plurality of clock speeds.
摘要翻译：一种被配置为提供包括一个或多个虚拟多队列FIFO的存储设备的电路。电路通常被配置为以多个时钟速度的优选时钟速度工作。

7. 发明申请

US20140317458A1 EMBEDDED RESILIENT BUFFER 有权
标题翻译：嵌入式电阻缓冲器
公开(公告)号：US20140317458A1
公开(公告)日：2014-10-23
申请号：US13867968
申请日：2013-04-22
申请人： Somnath Paul , Sriram R. Vangal
发明人： Somnath Paul , Sriram R. Vangal
IPC分类号： G06F11/07
CPC分类号： G06F11/0787 , G06F5/065 , G06F11/0757 , G06F11/0772 , G06F11/1407 , G06F11/1645 , G06F11/26 , G06F13/1673 , G06F13/1689 , G06F2205/067 , G11C29/003 , G11C29/023 , G11C29/028 , H03K19/00 , H04L1/00 , H04L2012/5681 , Y02D10/14
摘要： Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.
摘要翻译：描述了一种装置，包括：第一顺序单元; 与第一顺序单元并联耦合的第一队列，使得第一队列和第一顺序单元接收第一输入，用于对第一输入进行双倍采样的第一序列; 比较单元，用于接收来自第一顺序单元的输出; 以及由前一周期的写指针控制的第一选择单元，所述第一选择单元接收所述第一队列的每个存储单元的输出，其中所述第一选择单元生成用于由所述第一比较单元进行比较的输出。

8. 发明授权

US08094562B1 Transmission of a continuous datastream through a re-clocked frame-based transport network 有权
标题翻译：通过基于时钟的基于帧的传输网络传输连续的数据流
公开(公告)号：US08094562B1
公开(公告)日：2012-01-10
申请号：US11138617
申请日：2005-05-26
申请人： Jason Baumbach , Somnath Paul , Paul Scott
发明人： Jason Baumbach , Somnath Paul , Paul Scott
IPC分类号： H04L12/26
CPC分类号： H04J3/0632 , H03L7/0807 , H03L7/104 , H04L2007/045
摘要： A network interface to transport a continuous datastream over a frame-based transport network. The network interface includes a data input, an egress buffer circuit, a phase locked loop, and a data output. The data input receives frames carrying the continuous datastream from the frame-based transport network. The egress buffer circuit is coupled to buffer the continuous datastream and to generate a feedback signal based at least in part on a fill-level of the egress buffer. The phase locked loop is coupled to receive the feedback signal from the egress buffer and to recover a clock signal from the continuous datastream. The data output is coupled to output the data of the continuous datastream from the egress buffer circuit based on the clock signal.
摘要翻译：用于在基于帧的传输网络上传输连续数据流的网络接口。网络接口包括数据输入，出口缓冲电路，锁相环和数据输出。数据输入从基于帧的传输网络接收携带连续数据流的帧。耦合到出口缓冲器电路以缓冲连续数据流，并且至少部分地基于出口缓冲器的填充级别产生反馈信号。耦合锁相环以从出口缓冲器接收反馈信号并从连续数据流恢复时钟信号。数据输出被耦合以基于时钟信号从出口缓冲器电路输出连续数据流的数据。

9. 发明授权

US07073019B2 Method and apparatus for assembling non-aligned packet fragments over multiple cycles 失效
标题翻译：用于在多个周期内组装非对齐分组片段的方法和装置
公开(公告)号：US07073019B2
公开(公告)日：2006-07-04
申请号：US10317874
申请日：2002-12-11
申请人： Amitabha Banerjee , Somnath Paul
发明人： Amitabha Banerjee , Somnath Paul
IPC分类号： G06F12/00
CPC分类号： G06F5/01
摘要： A method and apparatus for assembling non-aligned packet fragments over multiple cycles is described. In one embodiment, the invention is a method. The method includes rotating a non-aligned data fragment within a rotate register based on a tail pointer of a prior data fragment to form a rotated data fragment. The method also includes outputting the rotated data fragment to a double width bus as a double width image of the rotated data fragment. The method further includes selectively copying the double width image of the rotated data fragment from the bus to a location logically following the prior data fragment in a destination register.
摘要翻译：描述了用于在多个周期上组装非对齐分组片段的方法和装置。在一个实施例中，本发明是一种方法。该方法包括基于先前数据片段的尾部指针旋转旋转寄存器内的非对齐数据片段以形成旋转的数据片段。该方法还包括将旋转的数据片段输出到双宽度总线作为旋转的数据片段的双倍宽度图像。该方法还包括将来自总线的旋转的数据片段的双倍宽度图像选择性地复制到逻辑上跟随目的地寄存器中的先前数据片段的位置。

10. 发明授权

US06948030B1 FIFO memory system and method 失效
标题翻译： FIFO存储器系统和方法
公开(公告)号：US06948030B1
公开(公告)日：2005-09-20
申请号：US10234680
申请日：2002-09-04
申请人： Jay Kishora Gupta , Amitabha Banerjee , Somnath Paul
发明人： Jay Kishora Gupta , Amitabha Banerjee , Somnath Paul
IPC分类号： G06F5/06 , G06F13/00
CPC分类号： G06F5/065
摘要： A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.
摘要翻译：用于多个输入通道的FIFO存储器系统具有耦合到通道输入信号的通道控制逻辑。指针和标志逻辑块耦合到通道控制逻辑的输出。存储器具有耦合到信道控制逻辑和指针和标志逻辑的地址总线。

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