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1. 发明申请

US20210358509A1 DIRECT MAPPING 有权
公开(公告)号：US20210358509A1
公开(公告)日：2021-11-18
申请号：US17443406
申请日：2021-07-26
申请人： Cirrus Logic International Semiconductor Ltd.
发明人： Shafagh Kamkar , Dylan A. Hester , Bruce E. Duewer
IPC分类号： G10L19/16 , H03M5/08 , H03M5/14 , G06F3/16 , G10L19/02 , G10L19/032 , G10L19/26
摘要： A single-bit audio stream can be converted to a modified single-bit audio stream with a constant edge rate while maintaining a modulation index of the original audio stream using direct mapping. With direct mapping, a pre-filter bank may be combined with a multi-bit symbol mapper to select symbols for the modified audio stream with a constant edge rate per symbol and the same modulation index as the original audio stream. The output of the pre-filter bank may be an audio stream with no consecutive full-scale symbols. Using the output of the pre-filter bank, a multi-bit symbol mapper may use the symbol selector to output a symbol with a constant edge rate per symbol and the same modulation index as the original signal. The symbols may be converted to an analog signal for reproduction of audio content using a transducer.

2. 发明授权

US09866239B1 Method and system for bi-phase mark coding (BMC) decoding 有权
公开(公告)号：US09866239B1
公开(公告)日：2018-01-09
申请号：US15364032
申请日：2016-11-29
申请人： NXP B.V.
发明人： Ronald Dean Smith , Xu Zhang , Mikhail Svoiski , Jason Ryan Ferguson
IPC分类号： H03M7/12 , H03M5/12 , H03M5/08
CPC分类号： H03M5/12 , G06F11/1679 , H03M5/02 , H03M5/04 , H03M5/08
摘要： Embodiments of methods and systems for BMC decoding are described. In an embodiment, a method for BMC decoding involves performing a unit interval estimation of a BMC encoded bit stream, locating a bit boundary of the BMC encoded bit stream based on the unit interval estimation and a known sequence in a preamble of the BMC encoded bit stream, and measuring a time duration across multiple bit transitions from the bit boundary and decoding the BMC encoded bit stream based on the time duration and the unit interval estimation.

3. 发明授权

US09172394B2 Signal conversion system and method 有权
标题翻译：信号转换系统及方法
公开(公告)号：US09172394B2
公开(公告)日：2015-10-27
申请号：US14382979
申请日：2013-03-06
申请人： Actiwave AB
发明人： Erik Lindahl , Pär Gunnars Risberg
IPC分类号： H03M5/08 , H03K9/08 , H03M3/00 , H04L25/49 , H03K7/08
CPC分类号： H03K7/08 , H03K9/08 , H03M3/506 , H03M5/08 , H04L25/4902
摘要： A signal conversion system and method for converting an input signal to a pulse width modulated signal is disclosed. The signal conversion system includes a sample rate converter coupled with an associated pulse width modulation (PWM) module. A hardware and power efficient signal conversion system for resampling an audio input signal with an arbitrary sample rate to a pulse width modulated output audio signal for use in an audio processor and/or reproduction is disclosed. The signal conversion system may be particularly suitable for use in a battery operated consumer electronics device.
摘要翻译：公开了一种用于将输入信号转换为脉宽调制信号的信号转换系统和方法。信号转换系统包括与相关联的脉宽调制（PWM）模块耦合的采样率转换器。公开了一种硬件和功率有效的信号转换系统，用于将具有任意采样率的音频输入信号重新采样到用于音频处理器和/或再现的脉宽调制输出音频信号。信号转换系统可能特别适用于电池供电的消费电子设备。

4. 发明授权

US08421652B2 Decoding circuit and decoding method thereof 有权
标题翻译：解码电路及其解码方法
公开(公告)号：US08421652B2
公开(公告)日：2013-04-16
申请号：US12915068
申请日：2010-10-29
申请人： Chun-Ting Kuo , Chun-Fu Lin , Cheng-Han Hsieh
发明人： Chun-Ting Kuo , Chun-Fu Lin , Cheng-Han Hsieh
IPC分类号： H03M5/08
CPC分类号： H03M7/006
摘要： A decoding circuit is adapted for decoding an input signal. The input signal includes at least a break and the time length of the break is a preset time. The decoding circuit includes a decoding unit and a detecting unit. The detecting unit detects whether the voltage level of the input signal is kept at a specific logic level for more than the preset time. If the input signal is kept at the specific logic level for more than the preset time, the detecting circuit, according to the voltage level of the specific logic level, outputs the input signal or the inverted input signal to the decoding unit so as to perform a decoding process.
摘要翻译：解码电路适于对输入信号进行解码。输入信号至少包括一个断点，断点的时间长度是预设的时间。解码电路包括解码单元和检测单元。检测单元检测输入信号的电压电平是否保持在特定逻辑电平超过预设时间。如果输入信号保持在特定逻辑电平超过预设时间，则检测电路根据特定逻辑电平的电压电平将输入信号或反相输入信号输出到解码单元，以执行一个解码过程。

5. 发明授权

US07724161B1 Truncation for three-level digital amplifier 有权
标题翻译：截断三电平数字放大器
公开(公告)号：US07724161B1
公开(公告)日：2010-05-25
申请号：US11942601
申请日：2007-11-19
申请人： Sasan Cyrusian
发明人： Sasan Cyrusian
IPC分类号： H03M5/08
CPC分类号： H03M5/08 , H03F3/217
摘要： A noise shaper truncates the widths of pulses it supplies to a pulse-width modulator whose pulse-width modulated signals control a tri-level amplifier. The amplifier is filterless and DC free. Pulses that are narrower than a predefined minimum width are eliminated by the noise shaper. Other pulses are subjected to an algorithm that includes a multitude of ranges, each range defined by a minimum pulse width characterizing a lower bound of that range and a maximum pulse width characterizing an upper bound of that range. Associated with each range is a number of clock cycles defining the modified width of a pulses whose detected width falls within that range. To ensure that delays associated with a feedback loop disposed in the amplifier are accounted for, the reference voltage of a comparator tracks an output voltage of an integrator. Both the comparator and integrator are disposed in the loop.
摘要翻译：噪声整形器将其提供给脉冲宽度调制器的脉冲宽度截断，其脉冲宽度调制信号控制三电平放大器。放大器无滤波，无直流。通过噪声整形器消除比预定义的最小宽度窄的脉冲。其他脉冲经受包括多个范围的算法，每个范围由表征该范围的下限的最小脉冲宽度和表征该范围的上限的最大脉冲宽度限定。与每个范围相关联的是多个时钟周期，其限定检测到的宽度落在该范围内的脉冲的修改宽度。为了确保与设置在放大器中的反馈回路相关联的延迟被考虑，比较器的参考电压跟踪积分器的输出电压。比较器和积分器均置于回路中。

6. 发明授权

US07701367B2 Digital signal decoding method 失效
标题翻译：数字信号解码方法
公开(公告)号：US07701367B2
公开(公告)日：2010-04-20
申请号：US12248904
申请日：2008-10-10
申请人： Sheng-Jie Sang , Liang-Yan Dai
发明人： Sheng-Jie Sang , Liang-Yan Dai
IPC分类号： H03M5/08
CPC分类号： H03M5/08
摘要： A computer-implemented method to decode a digital signal includes following steps. A micro control unit (MCU) receives a digital signal. The MCU reads a low voltage period of the digital signal and stores a time duration of the low voltage period into a first register as a value TL. The MCU reads next high voltage period of the digital signal and stores a time duration of the high voltage period into a second register as a value TH. The MCU reads the value TL of the first register and the value TH of the second register, and computes a ratio TR=TH/TL. The MCU compares the ratio TR with two predetermined values M and N, if TR=M, the decoded result is a logical “1.” If TR=N, the decoded result is a logical “0.”
摘要翻译：用于解码数字信号的计算机实现的方法包括以下步骤。微控制单元（MCU）接收数字信号。 MCU读取数字信号的低电压周期，并将低电压周期的持续时间存储到第一寄存器中作为值TL。 MCU读取数字信号的下一个高电压周期，并将高电压周期的持续时间存储到第二寄存器中作为值TH。 MCU读取第一寄存器的值TL和第二寄存器的值TH，并计算比率TR = TH / TL。如果TR = M，MCU将比率TR与两个预定值M和N进行比较，解码结果为逻辑“1”。如果TR = N，则解码结果为逻辑“0”。

7. 发明授权

US07626451B2 Data demodulation using an asynchronous clock 有权
标题翻译：使用异步时钟进行数据解调
公开(公告)号：US07626451B2
公开(公告)日：2009-12-01
申请号：US10649218
申请日：2003-08-26
申请人： Larry Kirn
发明人： Larry Kirn
IPC分类号： H03K9/08 , H03M5/08
CPC分类号： H04L25/4902
摘要： A method and accompanying circuitry for asynchronous data demodulation uses sorted pulsewidth measurement based on an asynchronous clock. Lock-on of the data stream by such a system is accomplished by measured pulsewidth, rather than inferred frequency. The method broadly comprises the steps of measuring a temporal aspect of the asynchronous clock, and locking onto the data stream in accordance with the measured periods. In the preferred embodiment, the temporal aspect is a ratio of measured periods. Conveniently, a ratio of 2:1 may be used.
摘要翻译：用于异步数据解调的方法和相关电路使用基于异步时钟的排序脉宽测量。通过这种系统锁定数据流是通过测量的脉冲宽度来实现的，而不是推断出的频率。该方法广泛地包括以下步骤：测量异步时钟的时间方面，并根据测量的周期锁定到数据流上。在优选实施例中，时间方面是测量周期的比率。方便地，可以使用2:1的比例。

8. 发明授权

US07515072B2 Method and apparatus for converting PCM to PWM 有权
标题翻译：将PCM转换为PWM的方法和装置
公开(公告)号：US07515072B2
公开(公告)日：2009-04-07
申请号：US10945625
申请日：2004-09-21
申请人： Ana Borisavljevic
发明人： Ana Borisavljevic
IPC分类号： H03M5/08
CPC分类号： H03M3/506 , H03M5/08 , H03M7/3022
摘要： A circuit for converting from an input serial pulse code modulated (PCM) digital signal to an output pulse width modulated (PWM) digital signal for driving a switching audio amplifier requiring a pulse width modulated input signal, the circuit comprising a sample rate converter receiving the input serial PCM digital signal at a first sampling frequency and converting the input serial PCM digital signal to a second serial PCM digital signal at a second frequency if the first sampling frequency is lower than the second frequency, a digital filter stage for up-sampling the second serial PCM digital signal to a third frequency and converting the second serial PCM digital signal to a parallel digital signal, a volume control stage receiving the parallel digital signal and generating a volume adjusted parallel digital signal in accordance with a digital volume command control signal, a digital cross-point estimator stage for calculating a cross-point between the volume adjusted parallel digital signal and a digital ramp signal and generating a parallel digital signal representing a desired pulse width modulation of the switching audio amplifier, a quantizing stage for quantizing the parallel digital signal representing the desired pulse width modulation into a quantized parallel digital signal representing the pulse width modulation to be applied to the switching audio amplifier; and a PWM generation stage for converting the quantized parallel digital signal into a PWM signal for driving the switching audio amplifier.
摘要翻译：一种用于从输入串行脉冲编码调制（PCM）数字信号转换为输出脉宽调制（PWM）数字信号的电路，用于驱动需要脉宽调制输入信号的开关音频放大器，该电路包括一个采样率转换器，以第一采样频率输入串行PCM数字信号，并且如果第一采样频率低于第二频率，则将输入串行PCM数字信号转换成第二串行PCM数字信号，第二采样频率低于第二频率;数字滤波器级将第二串行PCM数字信号转换为第三频率并将第二串行PCM数字信号转换为并行数字信号，音量控制级接收并行数字信号并根据数字音量指令控制信号产生音量调节的并行数字信号，一个数字交叉点估计器阶段，用于计算体积调整的并行数字之间的交叉点数字斜坡信号和数字斜坡信号，并产生表示开关音频放大器的期望脉冲宽度调制的并行数字信号;量化级，用于将表示所需脉冲宽度调制的并行数字信号量化为表示脉冲宽度的量化并行数字信号调制应用于开关音频放大器; 以及用于将量化的并行数字信号转换为用于驱动开关音频放大器的PWM信号的PWM生成级。

9. 发明申请

US20080297382A1 PULSE-WIDTH MODULATION OF PULSE-CODE MODULATED SIGNALS AT SELECTABLE OR DYNAMICALLY VARYING SAMPLE RATES 有权
标题翻译：脉冲代码调制信号在可选或动态变化率下的脉冲宽度调制
公开(公告)号：US20080297382A1
公开(公告)日：2008-12-04
申请号：US12127173
申请日：2008-05-27
申请人： Lars Risbo
发明人： Lars Risbo
IPC分类号： H03M5/08
CPC分类号： H03M5/08 , G10L19/10
摘要： Digital audio circuitry including modulation circuitry (35; 135) for generating a pulse-width modulated (PWM) signal from processed pulse-code modulated (PCM) audio signals. The modulation circuitry includes a duration quantizer function (32) that generates a sequence of duration values d(k) from received PCM samples, quantized to integer multiples of periods of a master PWM clock (CLKpwm). The duration quantizer function also produces a feedback PCM value x(k) from each quantized duration value d(k) that is applied to a loop filter (36), the output of which modifies the received PCM sample stream to suppress quantization noise. Transient effects caused by modulation or abrupt changes in the desired PWM period are suppressed by digitally filtering (34; 134) the PWM period sample stream.
摘要翻译：数字音频电路包括用于从经处理的脉码调制（PCM）音频信号产生脉冲宽度调制（PWM）信号的调制电路（35; 135）。调制电路包括持续时间量化器功能（32），其从接收的PCM采样生成持续时间值d（k）的序列，量化到主PWM时钟（CLKpwm）的周期的整数倍。持续时间量化器功能还从施加到环路滤波器（36）的每个量化持续时间值d（k）产生反馈PCM值x（k），其输出修改接收的PCM采样流以抑制量化噪声。通过PWM周期采样流的数字滤波（34; 134）来抑制由期望的PWM周期中的调制或突然变化引起的瞬态效应。

10. 发明授权

US07391346B1 Switching amplifier system and method 有权
标题翻译：开关放大器系统及方法
公开(公告)号：US07391346B1
公开(公告)日：2008-06-24
申请号：US11702269
申请日：2007-02-05
申请人： Michael Determan , Kamlesh Khilnani
发明人： Michael Determan , Kamlesh Khilnani
IPC分类号： H03M5/08 , H03M1/82 , H03K9/08
CPC分类号： H03M5/08 , H03F3/217 , H03F2200/03 , H03F2200/321 , H03F2200/351 , H03M3/506 , H03M7/3026 , H03M7/3042
摘要： A switching amplifier system and method is disclosed. In a particular embodiment, a pulse width modulation frame size is determined based on a sample rate of a digital input signal. Data associated with the first digital input signal is modified based on the pulse width modulation frame size. A pulse width modulation signal is generated in response to the modified data.
摘要翻译：公开了一种开关放大器系统和方法。在特定实施例中，基于数字输入信号的采样率来确定脉宽调制帧大小。与第一数字输入信号相关联的数据基于脉宽调制帧大小被修改。响应于修改的数据产生脉宽调制信号。

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