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21. 发明申请

US20100321840A1 Bottom source NMOS triggered zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS) 有权
标题翻译：底部源NMOS触发齐纳钳位用于配置超低电压瞬态电压抑制器（TVS）
公开(公告)号：US20100321840A1
公开(公告)日：2010-12-23
申请号：US12456555
申请日：2009-06-17
申请人： Madhur Bobde
发明人： Madhur Bobde
IPC分类号： H02H9/04 , H01L29/866 , H01L21/329
CPC分类号： H01L27/0266 , H01L29/732
摘要： A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer thereon. The TVS device further includes a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate wherein the drain region interfaces with the body region constituting a junction diode and the drain region encompassed in the body region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal. The gate may be shorted to the drain for configuring the BS-MOSFET transistor into a two terminal device with a gate-to-source voltage equal to a drain-to-source voltage. The drain/collector/cathode terminal disposed on top of the trench gate turns on the BS-MOSFET upon application of a threshold voltage of the BS-MOSFET thus triggering the bipolar transistor for clamping and suppressing a transient voltage substantially near a threshold voltage of the BS-MOSFET.
摘要翻译：支持在其上支撑外延层的半导体衬底上的低电压瞬变电压抑制（TVS）器件。 TVS器件还包括底源金属氧化物半导体场效应晶体管（BS-MOSFET），其包括被包围在设置在半导体衬底的顶表面附近的体区中的漏极区域围绕的沟槽栅极，其中漏极区域与构成结二极管的主体区域和包含在构成双极晶体管的外延层顶部的主体区域中的漏极区域，其中顶部电极设置在用作漏极/集电极端子的半导体的顶表面上，并且底部电极设置在用作源/发射极的半导体衬底的底表面。主体区域还包括电连接到主体到源短路连接的表面体接触区域，从而将身体区域连接到用作源极/发射极端子的底部电极。栅极可能短路到漏极，用于将BS-MOSFET晶体管配置为栅极至源极电压等于漏极 - 源极电压的双端子器件。设置在沟槽栅极顶部的漏极/集电极/阴极端子在施加BS-MOSFET的阈值电压时导通BS-MOSFET，因此触发双极晶体管用于钳位和抑制基本接近阈值电压的瞬态电压 BS-MOSFET。

22. 发明授权

US07842974B2 Gallium nitride heterojunction schottky diode 有权
标题翻译：氮化镓异质结肖特基二极管
公开(公告)号：US07842974B2
公开(公告)日：2010-11-30
申请号：US12388390
申请日：2009-02-18
申请人： TingGang Zhu
发明人： TingGang Zhu
IPC分类号： H01L29/47
CPC分类号： H01L29/872 , H01L29/08 , H01L29/2003 , H01L29/417
摘要： A gallium nitride based semiconductor diode includes a substrate, a GaN layer formed on the substrate, an AlGaN layer formed on the GaN layer where the GaN layer and the AlGaN layer forms a cathode region of the diode, a metal layer formed on the AlGaN layer forming a Schottky junction therewith where the metal layer forms an anode electrode of the diode, and a high barrier region formed in the top surface of the AlGaN layer and positioned under an edge of the metal layer. The high barrier region has a higher bandgap energy than the AlGaN layer or being more resistive than the AlGaN layer.
摘要翻译：氮化镓基半导体二极管包括基板，形成在基板上的GaN层，形成在GaN层和AlGaN层形成二极管阴极区域的GaN层上的AlGaN层，形成在AlGaN层上的金属层与金属层形成二极管的阳极电极和形成在AlGaN层的顶表面中并位于金属层的边缘下方的高阻挡区域形成肖特基结。高阻挡区域具有比AlGaN层更高的带隙能量或比AlGaN层更具阻性的能力。

23. 发明申请

US20100276779A1 Transient Voltage Suppressor Having Symmetrical Breakdown Voltages 有权
标题翻译：具有对称故障电压的瞬态电压抑制器
公开(公告)号：US20100276779A1
公开(公告)日：2010-11-04
申请号：US12433358
申请日：2009-04-30
申请人： Lingpeng Guan , Madhur Bobde , Anup Bhalla
发明人： Lingpeng Guan , Madhur Bobde , Anup Bhalla
IPC分类号： H01L29/06 , H01L21/34 , H01L21/265 , H01L21/76 , H01L21/20
CPC分类号： H01L29/861 , H01L27/0259 , H01L29/10 , H01L29/6609
摘要： A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.
摘要翻译：垂直瞬态电压抑制（TVS）器件包括：第一导电类型的半导体衬底，其中衬底被重掺杂;第一导电类型的外延层，形成在衬底上，外延层具有第一厚度;以及基极区形成在外延层中的第二导电类型，其中基极区位于外延层的中间区域中。基极区域和外延层在基极区域的两侧提供基本对称的垂直掺杂分布。在一个实施例中，通过高能量注入形成基极区域。在另一个实施例中，基底区形成为掩埋层。选择外延层和基极区域的掺杂浓度以将TVS器件配置为基于穿通二极管的TVS或雪崩模式TVS。

24. 发明授权

US07825508B2 Multi-die DC-DC buck power converter with efficient packaging 有权
标题翻译：多芯片DC-DC降压电源转换器，具有高效的封装
公开(公告)号：US07825508B2
公开(公告)日：2010-11-02
申请号：US11830996
申请日：2007-07-31
申请人： François Hébert , Allen Chang
发明人： François Hébert , Allen Chang
IPC分类号： H01L23/34
CPC分类号： H01L23/49562 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/16 , H01L2224/16245 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48472 , H01L2224/49111 , H01L2224/49171 , H01L2224/73257 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/12041 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/00012 , H01L2924/00 , H01L2224/32225 , H01L2224/45099 , H01L2224/05599 , H01L2224/0401
摘要： A DC-DC buck converter in multi-die package is proposed having an output inductor, a low-side Schottky diode and a high-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a first die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the first die pad via an insulating die bond. Alternatively, the first die pad is grounded. The vertical MOSFET is a top drain N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the first die pad. The PRC is attached atop the first die pad via a conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration.
摘要翻译：提出了具有由功率调节控制器（PRC）控制的输出电感器，低侧肖特基二极管和高侧垂直MOSFET的多管芯封装中的DC-DC降压转换器。多管芯封装包括第一管芯焊盘，肖特基二极管与垂直MOSFET并排放置在其上。 PRC管芯通过绝缘管芯接合连接在第一管芯焊盘顶上。或者，第一管芯焊盘接地。垂直MOSFET是顶漏N沟道FET，肖特基二极管管芯的基极是其阳极。肖特基二极管和垂直MOSFET堆叠在第一芯片焊盘的顶部。 PRC通过导电芯片键连接在第一裸片焊盘顶上。肖特基二极管管芯可以以倒装芯片的形式提供，阴极是其衬底。或者，肖特基二极管被提供有阳极作为其衬底而没有倒装芯片配置。

25. 发明授权

US07800170B1 Power MOSFET device with tungsten spacer in contact hole and method 有权
标题翻译：功能MOSFET器件与钨隔离器接触孔及方法
公开(公告)号：US07800170B1
公开(公告)日：2010-09-21
申请号：US12533319
申请日：2009-07-31
申请人： Zeng-Yi He , Xiao-Ming Sui , Jian Wang , Si-Jie Shen
发明人： Zeng-Yi He , Xiao-Ming Sui , Jian Wang , Si-Jie Shen
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/4941 , H01L29/66734
摘要： The present invention discloses a power MOSFET device with an added tungsten spacer in its contact hole, and manufacturing methods for the device. The features of the device are as follows: It includes trench gate isolated in trench and source/body contacts formed in the contact hole, and the tungsten spacer between Ti/TiN barrier layer and aluminum metal layer, the tungsten spacer is deposited on the bottom corners of the contact hole to cover its bottom corners. The addition of tungsten spacer to the bottom corners of the contact hole can effectively eliminate the presence of pits at the corners and junction spiking due to poor step-coverage of the Ti/TiN barrier layer otherwise leading to direct contact of silicon with aluminum. Thus, the present invention prevents a power MOSFET device from failures due to Idss leakage thus insuring high device quality and yield.
摘要翻译：本发明公开了一种在其接触孔中具有添加的钨隔离物的功率MOSFET器件，以及该器件的制造方法。该器件的特点如下：它包括沟槽隔离的沟槽栅和形成在接触孔中的源/体接触，以及在Ti / TiN阻挡层和铝金属层之间的钨隔离物，钨隔离物沉积在底部接触孔的角部覆盖其底角。在接触孔的底部拐角处添加钨隔离层可以有效地消除由于Ti / TiN阻挡层的梯级覆盖不良导致硅与铝直接接触的拐角处的凹点和结尖的存在。因此，本发明防止功率MOSFET器件由于Idss泄漏而发生故障，从而确保了高的器件质量和产量。

26. 发明申请

US20100207232A1 Gallium Nitride Semiconductor Device With Improved Forward Conduction 有权
标题翻译：具有改进的正向传导的氮化镓半导体器件
公开(公告)号：US20100207232A1
公开(公告)日：2010-08-19
申请号：US12388402
申请日：2009-02-18
申请人： TingGang Zhu
发明人： TingGang Zhu
IPC分类号： H01L29/872
CPC分类号： H01L29/2003 , H01L29/0692 , H01L29/417 , H01L29/872
摘要： A gallium nitride based semiconductor diode includes a substrate, a semiconductor body including a first heavily doped GaN layer and a second lightly doped GaN layer. The semiconductor body includes mesas projecting upwardly from a lower surface where each of the mesas includes the second GaN layer and a portion of the first GaN layer. Schottky contacts are formed on the upper surface of the mesas and ohmic contacts are formed on the lower surface of the semiconductor body. An insulating layer is formed over the Schottky and ohmic contacts and vias are formed in the insulating layer to the Schottky and Ohmic contacts. A first metal pad is formed in a third metal layer and over vias to the Schottky contacts to form an anode electrode. A second metal pad is formed in the third metal layer and over vias to the ohmic contacts to form a cathode electrode.
摘要翻译：氮化镓基半导体二极管包括衬底，包括第一重掺杂GaN层和第二轻掺杂GaN层的半导体本体。半导体主体包括从下表面向上突出的台面，其中每个台面包括第二GaN层和第一GaN层的一部分。在台面的上表面上形成肖特基接触，并且在半导体本体的下表面上形成欧姆接触。在肖特基和欧姆接触之上形成绝缘层，并且在绝缘层中形成通孔至肖特基和欧姆接触。第一金属焊盘形成在第三金属层中，并穿过肖特基触点，形成阳极电极。在第三金属层中形成第二金属焊盘，并且在通孔上形成第二金属焊盘以形成阴极电极。

27. 发明申请

US20100200920A1 Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection 有权
标题翻译：门极漏极（GD）钳位和ESD保护电路的配置用于电源器件击穿保护
公开(公告)号：US20100200920A1
公开(公告)日：2010-08-12
申请号：US12378039
申请日：2009-02-09
申请人： Yi Su , Anup Bhalla , Daniel Ng
发明人： Yi Su , Anup Bhalla , Daniel Ng
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L27/0255 , H01L27/0629 , H01L29/0615 , H01L29/0638 , H01L29/0646 , H01L29/0692 , H01L29/0696 , H01L29/66734 , H01L29/7803 , H01L29/7804 , H01L29/7808 , H01L29/7811 , H01L29/7815 , H01L29/8611 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.
摘要翻译：一种半导体功率器件，其被支撑在半导体衬底上，该半导体衬底包括多个晶体管单元，每个晶体管单元具有源极和漏极，栅极用于控制在源极和漏极之间传输的电流。半导体还包括在栅极和漏极之间串联连接的栅极 - 漏极（GD）钳位端接器，还包括串联连接到硅二极管的多个背对背多晶硅二极管，包括半导体中的并行掺杂的列衬底，其中平行掺杂的柱具有预定的间隙。掺杂的柱还包括U形弯曲柱，其将平行掺杂的柱的端部连接在一起，深度掺杂的阱设置在U形弯曲部的下方并吞噬。

28. 发明授权

US07585705B2 Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop 有权
公开(公告)号：US07585705B2
公开(公告)日：2009-09-08
申请号：US11947750
申请日：2007-11-29
申请人： Mengyu Pan , Zengyi He , Kaiyu Chen
发明人： Mengyu Pan , Zengyi He , Kaiyu Chen
IPC分类号： H01L21/20
CPC分类号： H01L29/7813 , H01L21/8221 , H01L27/0255 , H01L29/66734 , H01L29/7808 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes: a) Fabricate numerous trench MOSFETs on a wafer. b) Add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer. c) Add numerous ESD protection modules atop the Si3N4 isolation layer. d) Remove those portions of the Si3N4 isolation layer that are not beneath the ESD protection modules. In one embodiment, hydrofluoric acid is used as a first etchant for patterning the LTO while hot phosphoric acid is used as a second etchant for removing portions of the Si3N4 isolation layer.

29. 发明授权

US07564292B2 Device and method for limiting Di/Dt caused by a switching FET of an inductive switching circuit 有权
标题翻译：用于限制由感性开关电路的开关FET引起的Di / Dt的装置和方法
公开(公告)号：US07564292B2
公开(公告)日：2009-07-21
申请号：US11864686
申请日：2007-09-28
申请人： Sanjay Havanur
发明人： Sanjay Havanur
IPC分类号： H03K17/04
CPC分类号： H03K17/08142 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/49111 , H01L2224/49113 , H03K17/164
摘要： A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes:An auxiliary inductor in series with the main switching FET for inducing an auxiliary inductive voltage proportional to di/dt.An auxiliary FET in parallel with the main switching FET. The auxiliary FET gate is connected to produce a gate voltage equal to the auxiliary inductive voltage. When the di/dt tends to exceed a pre-determined maximum rate of decrease, the auxiliary FET produces an auxiliary current component counteracting further decrease of the di/dt.The main switching FET and the auxiliary FET can be formed from a single die with shared source and drain. The auxiliary inductor can be implemented as a parasitic inductance of an inherently required bonding wire connecting the main switching FET to its device terminal to simplify packaging with reduced cost.
摘要翻译：提出了一种用于限制由主开关FET在关断感应开关电路期间引起的di / dt的电路。用于限制di / dt的电路包括：与主开关FET串联的辅助电感器，用于感应与di / dt成比例的辅助感应电压。与主开关FET并联的辅助FET。辅助FET栅极被连接以产生等于辅助感应电压的栅极电压。当di / dt趋于超过预定的最大降低速率时，辅助FET产生辅助电流分量，以抵消di / dt的进一步降低。主开关FET和辅助FET可以由具有共用源极和漏极的单个管芯形成。辅助电感器可以实现为将主开关FET连接到其器件端子的固有需要的接合线的寄生电感，从而以低成本简化封装。

30. 发明授权

US09147586B2 Semiconductor package with connecting plate for internal connection 有权
标题翻译：半导体封装带连接板用于内部连接
公开(公告)号：US09147586B2
公开(公告)日：2015-09-29
申请号：US14083452
申请日：2013-11-19
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Jun Lu , Kai Liu , Yan Xun Xue
IPC分类号： H01L23/495 , H01L23/34 , H01L23/498 , H01L21/56 , H01L23/00 , H01L25/07 , H01L23/31
CPC分类号： H01L21/565 , H01L23/3107 , H01L23/49517 , H01L23/49524 , H01L23/49551 , H01L23/49562 , H01L23/49575 , H01L24/34 , H01L24/37 , H01L24/40 , H01L24/48 , H01L25/07 , H01L2224/32245 , H01L2224/37011 , H01L2224/37147 , H01L2224/4007 , H01L2224/40095 , H01L2224/40137 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73263 , H01L2224/73265 , H01L2224/8385 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.
摘要翻译：具有用于内部连接的连接板的半导体封装包括：多个芯片，每个芯片在顶表面上具有多个接触区域; 一个或多个连接板具有多个电隔离的连接板部分，每个连接板部分连接半导体芯片的接触区域。制造半导体封装的方法包括将一个或多个连接板连接到多个半导体芯片的步骤，施加模制材料以封装芯片和连接板，将连接板的多个连接板部分分开浅切割或磨削。

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