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1. 发明申请

US20170194492A9 BOTTOM SOURCE NMOS TRIGGERED ZENER CLAMP FOR CONFIGURING AN ULTRA-LOW VOLTAGE TRANSIENT VOLTAGE SUPPRESSOR (TVS) 审中-公开
公开(公告)号：US20170194492A9
公开(公告)日：2017-07-06
申请号：US14037205
申请日：2013-09-25
申请人： Madhur Bobde
发明人： Madhur Bobde
IPC分类号： H01L29/78 , H01L29/70 , H01L29/66
CPC分类号： H01L29/7827 , H01L21/8249 , H01L27/0716 , H01L29/66234 , H01L29/6628 , H01L29/66666 , H01L29/66734 , H01L29/70 , H01L29/732 , H01L29/7327 , H01L29/7804 , H01L29/7808 , H01L29/781 , H01L29/7813
摘要： A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal.

2. 发明授权

US09620614B2 Sawtooth electric field drift region structure for power semiconductor devices 有权
公开(公告)号：US09620614B2
公开(公告)日：2017-04-11
申请号：US14036696
申请日：2013-09-25
申请人： Madhur Bobde
发明人： Madhur Bobde
IPC分类号： H01L29/66 , H01L29/739 , H01L29/78 , H01L29/861 , H01L29/06 , H01L29/08 , H01L29/10
CPC分类号： H01L29/66333 , H01L29/0615 , H01L29/0634 , H01L29/0873 , H01L29/1095 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/8611
摘要： This invention discloses a semiconductor power device formed in a semiconductor substrate includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*ND*WN=q*NA*WP and a punch through condition of WP

3. 发明申请

US20160013265A1 SEMICONDUCTOR DEVICE WITH FIELD THRESHOLD MOSFET FOR HIGH VOLTAGE TERMINATION 审中-公开
标题翻译：具有用于高电压终止的场阈MOSFET的半导体器件
公开(公告)号：US20160013265A1
公开(公告)日：2016-01-14
申请号：US14329938
申请日：2014-07-12
申请人： Hamza Yilmaz , Madhur Bobde
发明人： Hamza Yilmaz , Madhur Bobde
IPC分类号： H01L29/06 , H01L29/739 , H01L29/78
CPC分类号： H01L29/0623 , H01L27/0823 , H01L27/088 , H01L29/0619 , H01L29/0638 , H01L29/404 , H01L29/407 , H01L29/7393 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/7823
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在重掺杂层上并具有活性电池区域和边缘终止区域的轻掺杂层。边缘终止区域包括多个P沟道MOSFET。通过将栅极连接到漏电极，当施加的电压等于或大于P沟道MOSFET晶体管的阈值电压Vt时，在边缘终端上形成的P沟道MOSFET晶体管顺序导通，从而优化电压被每个地区封锁

4. 发明申请

US20160005809A1 CONFIGURATION AND METHOD TO GENERATE SADDLE JUNCTION ELECTRIC FIELD IN EDGE TERMINATION 审中-公开
公开(公告)号：US20160005809A1
公开(公告)日：2016-01-07
申请号：US14298537
申请日：2014-06-06
申请人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
发明人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/06 , H01L21/761
CPC分类号： H01L29/0634 , H01L21/26513 , H01L21/761 , H01L29/0615 , H01L29/0619 , H01L29/6609 , H01L29/861
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

5. 发明授权

US09231050B1 Configuration and method to generate saddle junction electric field in edge termination 有权
公开(公告)号：US09231050B1
公开(公告)日：2016-01-05
申请号：US14298537
申请日：2014-06-06
申请人： Madhur Bobde , Lingping Guan , Anup Bhalla , Hamza Yilmaz
发明人： Madhur Bobde , Lingping Guan , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L27/088 , H01L29/06 , H01L21/761
CPC分类号： H01L29/0634 , H01L21/26513 , H01L21/761 , H01L29/0615 , H01L29/0619 , H01L29/6609 , H01L29/861
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

6. 发明申请

US20150162410A1 TERMINATION DESIGN BY METAL STRAPPING GUARD RING TRENCHES SHORTED TO A BODY REGION TO SHRINK TERMINATION AREA 审中-公开
标题翻译：终止设计通过金属捆绑护栏紧固到一个身体部位到收缩终止区域
公开(公告)号：US20150162410A1
公开(公告)日：2015-06-11
申请号：US14098538
申请日：2013-12-06
申请人： Karthik Padmanabhan , Madhur Bobde
发明人： Karthik Padmanabhan , Madhur Bobde
IPC分类号： H01L29/40 , H01L29/78 , H01L29/36
CPC分类号： H01L29/7802 , H01L29/0623 , H01L29/0878 , H01L29/1095 , H01L29/36 , H01L29/407 , H01L29/66712 , H01L29/78 , H01L29/7811
摘要： This invention discloses a semiconductor power device formed in a semiconductor substrate of a first conductivity type comprises an active cell area and a termination area surrounding the active cell area and disposed near edges of the semiconductor substrate. The termination area includes a plurality of trenches filled with a conductivity material forming a shield electrode and insulated by a dielectric layer along trench sidewalls and trench bottom surface wherein the trenches extending vertically through a body region of a second conductivity type near a top surface of the semiconductor substrate and further extending through a surface shield region of the first conductivity type. A dopant region of the second conductivity type disposed below the surface shield region extending across and surrounding a trench bottom portion of the trenches. At least a metal connector disposed above the top surface of the semiconductor substrates electrically connecting to the shield electrode of at least two trenches and shorted to the body region.
摘要翻译：本发明公开了一种形成在第一导电类型的半导体衬底中的半导体功率器件，包括有源电池区域和围绕有源电池区域的端接区域，并设置在半导体衬底的边缘附近。终端区域包括填充有形成屏蔽电极的导电材料的多个沟槽，并且沿着沟槽侧壁和沟槽底表面被电介质层绝缘，其中沟槽垂直延伸穿过第二导电类型的体区附近靠近顶部表面并且还延伸穿过第一导电类型的表面屏蔽区域。第二导电类型的掺杂剂区域设置在表面屏蔽区域的下方，延伸穿过并围绕沟槽的沟槽底部。至少一个金属连接器，设置在半导体衬底的顶表面之上，电连接到至少两个沟槽的屏蔽电极并且短路到身体区域。

7. 发明授权

US09048282B2 Dual-gate trench IGBT with buried floating P-type shield 有权
标题翻译：双栅极沟槽IGBT，埋入浮动P型屏蔽
公开(公告)号：US09048282B2
公开(公告)日：2015-06-02
申请号：US13831066
申请日：2013-03-14
申请人： Jun Hu , Madhur Bobde , Hamza Yilmaz
发明人： Jun Hu , Madhur Bobde , Hamza Yilmaz
IPC分类号： H01L29/66 , H01L29/739
CPC分类号： H01L29/7395 , H01L29/0623 , H01L29/0696 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/66333
摘要： A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.
摘要翻译：一种制造绝缘栅双极晶体管（IGBT）器件的方法，包括：1）制备具有第一导电类型的外延层的半导体衬底，该半导体衬底支撑在第二导电类型的半导体衬底上; 2）施加栅极沟槽掩模以打开第一沟槽和第二沟槽，随后形成栅极绝缘层以衬垫沟槽并用多晶硅层填充沟槽以形成第一沟槽栅极和第二沟槽栅极; 3）注入第一导电类型的掺杂剂以在外延层中形成上重掺杂区; 以及4）在所述第一沟槽栅极的顶部上形成平面栅极，并且将注入掩模施加到植入物体掺杂剂和源掺杂剂以在所述半导体衬底的顶表面附近形成体区域和源极区域。

8. 发明申请

US20150084117A1 BOTTOM SOURCE NMOS TRIGGERED ZENER CLAMP FOR CONFIGURING AN ULTRA-LOW VOLTAGE TRANSIENT VOLTAGE SUPPRESSOR (TVS) 审中-公开
标题翻译：底电源NMOS触发钳位钳位用于配置超低电压瞬态电压抑制器（TVS）
公开(公告)号：US20150084117A1
公开(公告)日：2015-03-26
申请号：US14037205
申请日：2013-09-25
申请人： Madhur Bobde
发明人： Madhur Bobde
IPC分类号： H01L29/78 , H01L29/70 , H01L29/66
CPC分类号： H01L29/7827 , H01L21/8249 , H01L27/0716 , H01L29/66234 , H01L29/6628 , H01L29/66666 , H01L29/66734 , H01L29/70 , H01L29/732 , H01L29/7327 , H01L29/7804 , H01L29/7808 , H01L29/781 , H01L29/7813
摘要： A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal.
摘要翻译：一种支撑在支撑外延层以形成底部源极金属氧化物半导体场效应晶体管（BS-MOSFET）的半导体衬底上的低电压瞬态电压抑制（TVS）器件，其包括被包围在体内的漏极区域包围的沟槽栅极区域设置在半导体衬底的顶表面附近。漏区与构成结二极管的体区接合。外延层顶部的漏极区域构成双极晶体管，其顶部电极设置在用作漏极/集电极端子的半导体的顶表面上，而底部电极设置在用作源极/集电极端子的半导体衬底的底表面上，发射电极。主体区域还包括电连接到主体到源短路连接的表面体接触区域，从而将身体区域连接到用作源极/发射极端子的底部电极。

9. 发明授权

US08981425B2 Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS) 有权
公开(公告)号：US08981425B2
公开(公告)日：2015-03-17
申请号：US13869869
申请日：2013-04-24
申请人： Madhur Bobde
发明人： Madhur Bobde
IPC分类号： H01L27/02 , H01L29/66 , H01L27/06 , H01L29/866 , H01L29/868
CPC分类号： H01L29/66106 , H01L27/0255 , H01L27/0629 , H01L27/0814 , H01L29/866
摘要： A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.

10. 发明授权

US08878292B2 Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method 有权
标题翻译：自对准开槽积分型场效应晶体管（AccuFET）结构及方法
公开(公告)号：US08878292B2
公开(公告)日：2014-11-04
申请号：US12074280
申请日：2008-03-02
申请人： François Hébert , Madhur Bobde , Anup Bhalla
发明人： François Hébert , Madhur Bobde , Anup Bhalla
IPC分类号： H01L29/739
CPC分类号： H01L29/7828 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/41766 , H01L29/456 , H01L29/66666
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件。半导体功率器件包括沟槽栅极，每个沟槽栅极具有在由侧壁间隔物围绕的半导体衬底的顶表面之上延伸的伸出栅极段。半导体功率器件还包括与基本上平行于沟槽栅极的侧壁间隔开的开口的槽。粘贴门区段还包括由侧壁间隔物围绕的绝缘材料构成的盖。阻挡金属层覆盖盖的顶表面并且覆盖在侧壁间隔物上并在槽的顶表面上方延伸。这些槽填充有与栅极段相同的栅极材料，用作附加栅电极，用于提供向沟槽栅极延伸的耗尽层，借此栅极与沟槽栅极之间的漂移区域完全耗尽栅极 - 漏极电压Vgs = 0伏。

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