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    • 22. 发明授权
    • System for programming a non-volatile memory cell
    • 用于编程非易失性存储单元的系统
    • US06795342B1
    • 2004-09-21
    • US10307667
    • 2002-12-02
    • Yi HeZhizheng LiuMark W. RandolphSameer S. Haddad
    • Yi HeZhizheng LiuMark W. RandolphSameer S. Haddad
    • G11C1604
    • G11C16/10G11C16/0475G11C16/0491
    • A system for programming a charge stored on a charge storage region of a dielectric charge trapping layer of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a positive source programming bias to a first bit line that is the source of the selected memory cell while applying a drain programming voltage to a second bit line that forms a drain junction with the channel region and while applying a positive voltage to a selected word line. The source voltage may be applied by coupling the source bit line to a voltage divider or by coupling the source bit line to a resistor which in turn is coupled to a ground. A negative programming bias may also be applied to the substrate and to unselected word lines.
    • 一种用于对存储在双位介质存储器单元阵列内的第一双位介质存储单元的介电电荷俘获层的电荷存储区域上的电荷进行编程的系统包括将正源编程偏置施加到第一位线 同时将漏极编程电压施加到与沟道区形成漏极结的第二位线以及向所选择的字线施加正电压的所选存储单元的源极。 可以通过将源极线耦合到分压器或通过将源极线耦合到电阻器来施加源极电压,电阻器又连接到地电位器。 负编程偏置也可以应用于衬底和未选择的字线。
    • 23. 发明授权
    • Source drain implant during ONO formation for improved isolation of SONOS devices
    • 在ONO形成期间的源极漏极注入,以改善SONOS器件的隔离
    • US06436768B1
    • 2002-08-20
    • US09893279
    • 2001-06-27
    • Jean Yee-Mei YangMark T. RamsbeyEmmanuil Manos LingunisYider WuTazrien KamalYi HeEdward HsiaHidehiko Shiraiwa
    • Jean Yee-Mei YangMark T. RamsbeyEmmanuil Manos LingunisYider WuTazrien KamalYi HeEdward HsiaHidehiko Shiraiwa
    • H01L21336
    • H01L21/2652H01L21/2658H01L27/11568H01L29/66833
    • One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.
    • 本发明的一个方面涉及一种形成SONOS型非易失性半导体存储器件的方法,包括在半导体衬底上形成电荷俘获电介质的第一层; 在所述半导体衬底上的所述电荷俘获电介质的所述第一层上形成所述电荷俘获电介质的第二层; 可选地至少部分地在所述半导体衬底上的所述电荷俘获电介质的所述第二层上形成所述电荷俘获电介质的第三层; 任选地去除电荷俘获电介质的第三层; 在电荷俘获电介质上形成源极/漏极掩模; 将源极/漏极注入物通过电荷俘获电介质注入到半导体衬底中; 任选地去除电荷俘获电介质的第三层; 以及在半导体衬底上的电荷俘获电介质的第二层上形成电荷俘获电介质的第三层之一,在半导体衬底上的电荷俘获电介质的第二层上重整第三层电荷俘获电介质,或 在电荷俘获电介质的第三层上形成附加材料。
    • 24. 发明授权
    • N-channel multi-time programmable memory devices
    • N通道多时间可编程存储器件
    • US08975685B2
    • 2015-03-10
    • US13600792
    • 2012-08-31
    • Yi HeXiang LuAlbert Bergemont
    • Yi HeXiang LuAlbert Bergemont
    • H01L29/788
    • G11C16/0408G11C2216/10
    • N-channel multi-time programmable memory devices having an N-conductivity type substrate, first and second P-conductivity type wells in the N-conductivity type substrate, N-conductivity type source and drain regions formed in the first P-conductivity type well, the source and drain regions being separated by a channel region, an oxide layer over the N-conductivity type substrate; and a floating gate extending over the channel region and over the second P-conductivity type well in the N-conductivity type substrate, the multi-time programmable memory cell being programmable by hot electron injection and erasable by hot hole injection.
    • 具有N-导电类型衬底,N导电类型衬底中的第一和第二P导电类型阱的N沟道多时间可编程存储器件,形成在第一P导电型阱中的N导电型源极和漏极区 源极和漏极区域被沟道区域分隔,N导电型衬底上的氧化物层; 以及在N导电类型衬底中在沟道区域上延伸超过第二P导电类型的浮栅,多时间可编程存储单元可通过热电子注入进行编程,并可通过热空穴注入进行擦除。
    • 27. 发明授权
    • Controller for a resonant switched-mode power converter
    • 谐振开关型功率转换器的控制器
    • US08456868B2
    • 2013-06-04
    • US12771467
    • 2010-04-30
    • Yi HeTuck Meng ChanYong Siang TeoXiaowu GongMeng Kiat Jeoh
    • Yi HeTuck Meng ChanYong Siang TeoXiaowu GongMeng Kiat Jeoh
    • H02M3/335
    • H02M3/3378H02M3/33592H02M2001/0058Y02B70/1433Y02B70/1475Y02B70/1491
    • An embodiment of the invention relates to an LLC power converter including a controller configured to regulate an output characteristic of the power converter by controlling a power converter switching frequency. In a first mode of operation, the controller turns off a secondary-side power switch earlier than a turn-off time of a primary-side power switch by a time difference that is controlled by a resistor coupled to an external circuit node. In a second mode of operation, the controller turns on a secondary-side power switch at substantially the same time as the primary-side power switch, and turns off the secondary-side power switch after a maximum on time that is a nonlinear function of a load current of the power converter. The nonlinear function is a substantially constant function of the load current for a value of the load current higher than a threshold value.
    • 本发明的实施例涉及一种LLC功率转换器,其包括被配置为通过控制功率转换器开关频率来调节功率转换器的输出特性的控制器。 在第一操作模式中,控制器比次级侧电源开关早于初级侧电源开关的关断时间,该时间差由耦合到外部电路节点的电阻器控制。 在第二操作模式中,控制器在与初级侧电源开关基本相同的时间接通次级侧电源开关,并且在作为非线性功能的最大导通时间之后关闭次级侧电源开关 功率转换器的负载电流。 对于高于阈值的负载电流的值,非线性函数是负载电流的基本上恒定的函数。