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1. 发明授权

US06999885B2 System and method for processing a periodic or cyclostationary signal 有权
标题翻译：用于处理周期性或循环平稳信号的系统和方法
公开(公告)号：US06999885B2
公开(公告)日：2006-02-14
申请号：US10825034
申请日：2004-04-15
申请人： Howard Hilton
发明人： Howard Hilton
IPC分类号： G01R29/00 , G06F19/00
CPC分类号： G01R13/0254
摘要： In one representative embodiment, multiple ensembles of samples of a periodic or cylcostationary signal are processed in a time aligned manner. The sampling rate of the processing system is adjusted so that an integer number of sampling intervals equals the period of the signal. A cyclic counter is programmed to reset according to the integer number. Also, the cyclic counter may be initialized according to an external trigger. During operation, the cyclic counter is incremented when each sample is received. Continuous operation of the cyclic counter with the capturing of samples enables precise time alignment between ensembles of samples. Specifically, the beginning of a discrete ensemble is identified by a reset of the cyclic counter. Because each ensemble is time aligned, further processing (e.g., coherent averaging) may occur without post-processing to time-shift each sample to achieve the time alignment.
摘要翻译：在一个代表性实施例中，以时间对齐的方式处理周期性或平稳信号的多个样本集合。调整处理系统的采样率，使得整数个采样间隔等于信号的周期。循环计数器被编程为根据整数复位。此外，可以根据外部触发来初始化循环计数器。在运行期间，当接收到每个样本时，循环计数器递增。循环计数器的连续操作与样品的捕获可以在样品集合之间进行精确的时间对准。具体来说，通过循环计数器的复位来识别离散集合的开始。因为每个集合是时间对齐的，所以可以进行进一步处理（例如，相干平均），而不需要后处理来对每个样本进行时移以实现时间对准。

2. 发明申请

US20050143982A1 Method and system for accelerating power complementary cumulative distribution function measurements 失效
标题翻译：加速功率互补累积分布函数测量的方法和系统
公开(公告)号：US20050143982A1
公开(公告)日：2005-06-30
申请号：US10737050
申请日：2003-12-15
申请人： Yi He , Gerald Ringel , Howard Hilton , Brian Barton
发明人： Yi He , Gerald Ringel , Howard Hilton , Brian Barton
IPC分类号： G06F15/00 , G06F17/18
CPC分类号： G06F17/18 , G01R21/133
摘要： Data values representing the (I2+Q2) values are converted to floating-point representations and a histogram of the floating-point numbers is generated. The count for each histogram bin in the histogram is stored in a memory. Each floating-point number acts as an address for a corresponding histogram bin in the memory. The accumulated counts in the histogram bins are then grouped into a desired number of CCDF bins, and the CCDF curve is derived from the histogram data. Grouping the histogram bins into the CCDF bins may include combining one or more histogram bins into a single CCDF bin. Linear interpolation is used to divide a count value in a histogram bin between two CCDF bins when the histogram bin does not align with a single CCDF bin.
摘要翻译：表示（I＆lt; 2＆gt; +＆lt; 2＆gt; 2）值的数据值被转换为浮点表示，并且生成浮点数的直方图。直方图中每个直方图单元格的计数都存储在存储器中。每个浮点数作为存储器中对应的直方图bin的地址。然后将直方图区块中的累积计数分组为所需数量的CCDF仓，并从直方图数据中导出CCDF曲线。将直方图箱分组到CCDF箱中可以包括将一个或多个直方图箱组合成单个CCDF箱。线性插值用于在直方图单元不与单个CCDF模块对齐时，在两个CCDF模块之间的直方图存储区中计算计数值。

3. 发明申请

US20050132164A1 Pipelined accumulators 有权
标题翻译：流水线蓄能器
公开(公告)号：US20050132164A1
公开(公告)日：2005-06-16
申请号：US10677995
申请日：2003-10-01
申请人： George Moore , John Snodderley , Howard Hilton
发明人： George Moore , John Snodderley , Howard Hilton
IPC分类号： G06F7/509 , G06F15/00 , G06F15/76
CPC分类号： G06F7/5095 , G06F2207/3884
摘要： Pipelined digital accumulators. Parallel digital accumulators for use in digital signal processing are improved through pipelining. An accumulator is partitioned into a plurality of pipelined stages, and the pipeline delay is used to reduce the effect of carry propagation through the accumulator. While input and output delay registers are used in the accumulator partitions, the output delay registers are not needed if the results of those partitions are not needed in subsequent stages of computation. If phase coherence is not needed, input delay registers may not be needed on accumulator partitions. In the limiting case of one bit per partition, the effective speed of the pipelined accumulator is equivalent to the speed of a single bit accumulator stage.
摘要翻译：流水线数字蓄能器。通过流水线改进用于数字信号处理的并行数字累加器。累加器被划分成多个流水线级，并且使用流水线延迟来减少通过累加器的进位传播的影响。虽然在累加器分区中使用输入和输出延迟寄存器，但是如果在后续的计算阶段不需要这些分区的结果，则不需要输出延迟寄存器。如果不需要相位相干，则在累加器分区上可能不需要输入延迟寄存器。在每个分区一位的限制情况下，流水线累加器的有效速度等于单位累加器级的速度。

4. 发明授权

US08243714B1 Method and apparatus for hierarchial system synchronization 有权
标题翻译：分层系统同步的方法和装置
公开(公告)号：US08243714B1
公开(公告)日：2012-08-14
申请号：US12115100
申请日：2008-05-05
申请人： Howard Hilton , Darrin Dennis Rath , Gerald J. Ringel
发明人： Howard Hilton , Darrin Dennis Rath , Gerald J. Ringel
IPC分类号： H04J3/06
CPC分类号： H04J3/0685 , G06F2213/0038 , H04L7/0008
摘要： An apparatus includes a global synchronization interface and multiple modules. The global synchronization interface includes a global synchronization driver for driving a global synchronization signal. The modules include corresponding local synchronization interfaces, each local synchronization interface having a local synchronization driver for driving a local synchronization signal. In a local mode, the modules ignore the global synchronization signal and synchronize corresponding operations according to the local synchronization signal and a global reference signal. In a global mode, the modules ignore the local synchronization signal and synchronize the corresponding operations according to the global synchronization signal and the global reference signal.
摘要翻译：一种装置包括全局同步接口和多个模块。全局同步接口包括用于驱动全局同步信号的全局同步驱动器。模块包括相应的本地同步接口，每个本地同步接口具有用于驱动本地同步信号的本地同步驱动器。在本地模式下，模块忽略全局同步信号，并根据本地同步信号和全局参考信号同步相应的操作。在全局模式下，模块忽略本地同步信号，并根据全局同步信号和全局参考信号使相应的操作同步。

5. 发明申请

US20060092056A1 SAMPLE RATE DOUBLING USING ALTERNATING ADCS 有权
标题翻译：使用替代ADCS的采样速率倍增
公开(公告)号：US20060092056A1
公开(公告)日：2006-05-04
申请号：US10977833
申请日：2004-10-29
申请人： Howard Hilton
发明人： Howard Hilton
IPC分类号： H03M1/06
CPC分类号： H03M1/0626 , H03M1/1215
摘要： One embodiment of the invention includes a system comprising an analog baseband signal input, a conversion circuit with N Analog to Digital Converters (ADCs) operable to receive the analog baseband signal, and a Finite Impulse Response (FIR) filter operable to receive outputs of the N ADCs and to produce a digital representation of the analog baseband signal corrected for a mismatch in the N ADCs.
摘要翻译：本发明的一个实施例包括一种包括模拟基带信号输入的系统，具有可操作以接收模拟基带信号的N个模数转换器（ADC）的转换电路和可操作以接收所述模拟基带信号的输出的有限脉冲响应（FIR）滤波器 N个ADC，并产生针对N个ADC中的失配校正的模拟基带信号的数字表示。

6. 发明申请

US20050234667A1 System and method for processing a periodic or cyclostationary signal 有权
标题翻译：用于处理周期性或循环平稳信号的系统和方法
公开(公告)号：US20050234667A1
公开(公告)日：2005-10-20
申请号：US10825034
申请日：2004-04-15
申请人： Howard Hilton
发明人： Howard Hilton
IPC分类号： G01R13/20 , G01R13/02 , G01R23/02 , G06F15/00 , G06F19/00
CPC分类号： G01R13/0254
摘要： In one representative embodiment, multiple ensembles of samples of a periodic or cylcostationary signal are processed in a time aligned manner. The sampling rate of the processing system is adjusted so that an integer number of sampling intervals equals the period of the signal. A cyclic counter is programmed to reset according to the integer number. Also, the cyclic counter may be initialized according to an external trigger. During operation, the cyclic counter is incremented when each sample is received. Continuous operation of the cyclic counter with the capturing of samples enables precise time alignment between ensembles of samples. Specifically, the beginning of a discrete ensemble is identified by a reset of the cyclic counter. Because each ensemble is time aligned, further processing (e.g., coherent averaging) may occur without post-processing to time-shift each sample to achieve the time alignment.
摘要翻译：在一个代表性实施例中，以时间对齐的方式处理周期性或平稳信号的多个样本集合。调整处理系统的采样率，使得整数个采样间隔等于信号的周期。循环计数器被编程为根据整数复位。此外，可以根据外部触发来初始化循环计数器。在运行期间，当接收到每个样本时，循环计数器递增。循环计数器的连续操作与样品的捕获可以在样品集合之间进行精确的时间对准。具体来说，通过循环计数器的复位来识别离散集合的开始。因为每个集合是时间对齐的，所以可以进行进一步处理（例如，相干平均），而不需要后处理来对每个样本进行时移以实现时间对准。

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