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21. 发明授权

US07368302B2 Dynamic metal fill for correcting non-planar region 有权
标题翻译：用于校正非平面区域的动态金属填充
公开(公告)号：US07368302B2
公开(公告)日：2008-05-06
申请号：US10908128
申请日：2005-04-28
申请人： Stephen E. Greco
发明人： Stephen E. Greco
IPC分类号： H01L21/00
CPC分类号： H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Methods and a system are disclosed for correcting a non-planar region during fabrication of a semiconductor product on a wafer. The invention separates an exposure of at least a portion of a fill pattern on a resist from a product exposure so that the fill pattern can be adjusted to correct the non-planar region. In one embodiment, a determination of whether a fill pattern for a metal level above the non-planar region includes a portion over the non-planar region is made. Where a portion of the fill pattern is to be placed over the non-planar region, a pattern factor for exposure of the portion of the fill pattern on a resist is adjusted to correct the non-planar region.
摘要翻译：公开了用于在晶片上制造半导体产品期间校正非平面区域的方法和系统。本发明将抗蚀剂上的填充图案的至少一部分的曝光与产品曝光分开，使得可以调整填充图案以校正非平面区域。在一个实施例中，确定在非平面区域之上的金属水平的填充图案是否包括非平面区域上的部分。在填充图案的一部分被放置在非平面区域上的情况下，调整填充图案的部分在抗蚀剂上的曝光的图案因子以校正非平面区域。

22. 发明授权

US07071099B1 Forming of local and global wiring for semiconductor product 有权
标题翻译：形成半导体产品的本地和全球接线
公开(公告)号：US07071099B1
公开(公告)日：2006-07-04
申请号：US10908623
申请日：2005-05-19
申请人： Stephen E. Greco , Theodorus E. Standaert
发明人： Stephen E. Greco , Theodorus E. Standaert
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76807 , H01L21/76838 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming different back-end-of-line (BEOL) wiring for different circuits on the same semiconductor product, i.e., wafer or chip, are disclosed. In one embodiment, the method includes simultaneously generating BEOL wiring over a first circuit using a dual damascene structure in a first dielectric layer, and BEOL wiring over a second circuit using a single damascene via structure in the first dielectric layer. Then, simultaneously generating BEOL wiring over the first circuit using a dual damascene structure in a second dielectric layer, and BEOL wiring over the second circuit using a single damascene line wire structure in the second dielectric layer. The single damascene via structure has a width approximately twice that of a via portion of the dual damascene structures and the single damascene line wire structure has a width approximately twice that of a line wire portion of the dual damascene structures. A semiconductor product having different width BEOL wiring for different circuits is also disclosed.
摘要翻译：公开了在同一半导体产品即晶片或芯片上形成用于不同电路的不同后端线（BEOL）布线的方法。在一个实施例中，该方法包括使用第一电介质层中的双镶嵌结构在第一电路上同时产生BEOL布线，以及使用第一电介质层中的单镶嵌通孔结构的第二电路上的BEOL布线。然后，使用第二电介质层中的双镶嵌结构同时在第一电路上产生BEOL布线，并且在第二电介质层中使用单个镶嵌线线结构在第二电路上生成BEOL布线。单个镶嵌通孔结构的宽度大约是双镶嵌结构的通孔部分的宽度的两倍，并且单镶嵌线结构的宽度大约是双镶嵌结构的线丝部分的宽度的两倍。还公开了一种用于不同电路的具有不同宽度的BEOL布线的半导体产品。

23. 发明授权

US06221780B1 Dual damascene flowable oxide insulation structure and metallic barrier 失效
标题翻译：双镶嵌可流动氧化物绝缘结构和金属屏障
公开(公告)号：US06221780B1
公开(公告)日：2001-04-24
申请号：US09408351
申请日：1999-09-29
申请人： Stephen E. Greco , John P. Hummel , Joyce Liu , Vincent J. McGahay , Rebecca Mih , Kamalesh Srivastava
发明人： Stephen E. Greco , John P. Hummel , Joyce Liu , Vincent J. McGahay , Rebecca Mih , Kamalesh Srivastava
IPC分类号： H01L21311
CPC分类号： H01L21/76843 , H01L21/31116 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/7684
摘要： A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.
摘要翻译：一种通过氧化FOX绝缘体的侧壁来保护半导体中的可流动的氧化物绝缘体的方法和结构，可选地将氧化的FOX侧壁氮化，然后覆盖包括侧壁在内的FOX绝缘体中的槽或多个槽的所有表面，导电二级保护层。在多层镶嵌结构中，FOX绝缘体的表面也被氧化，在其上沉积另外的氧化物层，并且沉积在氧化物层上的氮化物层。然后重复步骤以获得可比较的镶嵌结构。材料可以变化，并且每个镶嵌层可以是单镶嵌层或双镶嵌层。

24. 发明授权

US5444015A Larce scale IC personalization method employing air dielectric structure for extended conductors 失效
标题翻译： Larce尺寸IC个性化方法采用空气电介质结构用于扩展导体
公开(公告)号：US5444015A
公开(公告)日：1995-08-22
申请号：US225685
申请日：1994-04-11
申请人： John M. Aitken , Klaus D. Beyer , Billy L. Crowder , Stephen E. Greco
发明人： John M. Aitken , Klaus D. Beyer , Billy L. Crowder , Stephen E. Greco
IPC分类号： H01L27/04 , H01L21/768 , H01L21/822 , H01L23/522 , H01L21/28
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002
摘要： Fabrication methods for forming a network of walls concurrently with the formation of studs for interconnecting plural device layers of a large scale integrated circuit device permits aggressive reduction of the average dielectric constant of air dielectric structures. Wall sections may be positioned to laterally support high aspect ratio connecting studs with a network of open or closed polygons. Wall patterns may also be open from layer to layer to allow formation of large scale air dielectric structures over a plurality of layers in a single material removal step. A wide range of shear strengths and reductions of average dielectric constant can be achieved even within a single device layer of a large scale integrated circuit and exploited to meet circuit design and device fabrication process requirements.
摘要翻译：用于形成用于互连大规模集成电路器件的多个器件层的螺柱的壁的形成网络的制造方法允许大大降低空气电介质结构的平均介电常数。壁部分可以被定位成横向支撑具有开放或闭合多边形网络的高纵横比连接螺柱。壁图案也可以从一层开放，以允许在单个材料去除步骤中在多个层上形成大规模空气介电结构。即使在大规模集成电路的单个器件层内，也可以获得宽范围的剪切强度和平均介电常数的降低，并被用于满足电路设计和器件制造工艺要求。

25. 发明授权

US07941780B2 Intersect area based ground rule for semiconductor design 有权
标题翻译：半导体设计相交区域基准规则
公开(公告)号：US07941780B2
公开(公告)日：2011-05-10
申请号：US12105299
申请日：2008-04-18
申请人： Albrik Avanessian , Henry A. Bonges, III , Dureseti Chidambarrao , Stephen E. Greco , Douglas W. Kemerer , Tina Wagner
发明人： Albrik Avanessian , Henry A. Bonges, III , Dureseti Chidambarrao , Stephen E. Greco , Douglas W. Kemerer , Tina Wagner
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.
摘要翻译：提供了一种设计规则，其通过估计半导体芯片中的对应结构的物理重叠区域或“交叉区域”来确定两个相邻级别中的两个设计元素之间的重叠程度。物理相交区域的估计可以考虑线边缘偏置，临界尺寸公差，覆盖公差和角舍入，以提供对应于两个设计元素的每个结构的物理面积的精确估计。采用交叉区域作为度量以确定是否符合基本规则，即基于交叉区域来指定接地规则。可以从交叉区域计算其他衍生量，例如电阻，电迁移阻力，预期产量，并且可以有利地用于优化设计数据。

26. 发明申请

US20100032846A1 IC HAVING VIABAR INTERCONNECTION AND RELATED METHOD 有权
标题翻译：具有VIABAR互连的IC和相关方法
公开(公告)号：US20100032846A1
公开(公告)日：2010-02-11
申请号：US12186061
申请日：2008-08-05
申请人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
发明人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.
摘要翻译：一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar，在第二位置处连接到第一金属层的布线而不是第二金属层的布线。

27. 发明申请

US20080179709A1 INTEGRATED CIRCUIT FUSE 有权
标题翻译：集成电路保险丝
公开(公告)号：US20080179709A1
公开(公告)日：2008-07-31
申请号：US12054876
申请日：2008-03-25
申请人： Stephen E. Greco
发明人： Stephen E. Greco
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L21/7682 , H01L21/76892 , H01L2924/0002 , Y10S430/146 , H01L2924/00
摘要： An integrated circuit and a fuse therefore are disclosed. The integrated circuit fuses includes a plurality of terminals coupled by a fuse element, wherein the fuse element is located in a non-last metal layer and/or wherein each terminal is fully-landed on an upper surface of a wire of the fuse element. As a result, there is no explosion that causes damage to surrounding material. In addition, use of the wet etchant allows positioning of a fuse in any metal layer including any non-last metal layer, thus increasing design possibilities.
摘要翻译：因此，公开了集成电路和保险丝。集成电路熔断器包括由熔丝元件耦合的多个端子，其中熔丝元件位于非最后金属层和/或其中每个端子完全降落在熔丝元件的导线的上表面上。因此，没有爆炸造成周围材料的损坏。此外，使用湿蚀刻剂允许在包括任何非最后金属层的任何金属层中定位熔丝，从而增加设计可能性。

28. 发明授权

US07323410B2 Dry etchback of interconnect contacts 有权
标题翻译：互连触点的干蚀刻
公开(公告)号：US07323410B2
公开(公告)日：2008-01-29
申请号：US11161538
申请日：2005-08-08
申请人： Theodorus E. Standaert , William H. Brearley , Stephen E. Greco , Sujatha Sankaran
发明人： Theodorus E. Standaert , William H. Brearley , Stephen E. Greco , Sujatha Sankaran
IPC分类号： H01L21/44
CPC分类号： H01L21/76808 , H01L21/31116 , H01L21/32136 , H01L21/76847 , H01L21/76877 , H01L21/76883 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.
摘要翻译：具有降低的接触电阻和改善的可靠性的复合螺柱接触界面的方法和结构。使用包含含氟气体的选择性干蚀刻。在M1 RIE工艺过程中或之后，通过部分干法蚀刻钨触点来降低接触电阻。然后在M1衬套/电镀工艺期间将凹陷接触件金属化。钨接触高度在完全成型后减小。

29. 发明授权

US07301236B2 Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via 有权
标题翻译：使用垂直向上延伸的虚拟通孔增加IC中的电迁移寿命和电流密度
公开(公告)号：US07301236B2
公开(公告)日：2007-11-27
申请号：US11163410
申请日：2005-10-18
申请人： Stephen E. Greco , Chao-Kun Hu , Paul S. McLaughlin
发明人： Stephen E. Greco , Chao-Kun Hu , Paul S. McLaughlin
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.
摘要翻译：公开了一种具有增加的电迁移寿命和允许电流密度的集成电路及其形成方法。在一个实施例中，集成电路包括连接到至少一个功能通孔的导线，以及至少一个虚拟通孔，其具有与导电线电连接的第一下端，以及电连接（隔离）至任何导电线。每个虚拟通孔从导电线垂直向上延伸，并且去除快速扩散路径的一部分，即金属到电介质盖界面，其被金属对金属衬垫界面代替。因此，每个虚拟通孔可以减少金属扩散速率，从而增加电迁移寿命并允许增加电流密度。

30. 发明授权

US07101784B2 Method to generate porous organic dielectric 失效
标题翻译：生成多孔有机电介质的方法
公开(公告)号：US07101784B2
公开(公告)日：2006-09-05
申请号：US11125549
申请日：2005-05-10
申请人： Lawrence A. Clevenger , Stephen E. Greco , Keith T. Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong H. Wong
发明人： Lawrence A. Clevenger , Stephen E. Greco , Keith T. Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong H. Wong
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76835 , H01L21/76856 , H01L2221/1036
摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).
摘要翻译：本发明提供一种形成集成电路结构中的布线层的方法，该集成电路结构形成有机绝缘体，图案化绝缘体，将衬垫沉积在绝缘体上，并将该结构暴露于等离子体，以在绝缘体旁边的区域中形成孔衬垫。衬垫形成得足够薄以允许等离子体穿过衬垫并在绝缘体中形成孔。在等离子体处理期间，等离子体通过衬垫而不影响衬垫。在等离子体处理之后，可以沉积另外的衬里材料。此后，导体被沉积，导体的多余部分从结构中移除，使得导体仅保留在绝缘体的图案化部分内。该方法产生集成电路结构，其具有具有图案化特征的有机绝缘体，衬里图案化特征的衬垫和填充图案化特征的导体。绝缘体包括与绝缘体的表面区域相接触的孔，该孔与衬垫接触，并且孔仅沿着与衬垫接触的表面区域（衬里不在孔内）存在。

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