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1. 发明授权

US06531069B1 Reactive Ion Etching chamber design for flip chip interconnections 失效
标题翻译：反向离子蚀刻室设计用于倒装芯片互连
公开(公告)号：US06531069B1
公开(公告)日：2003-03-11
申请号：US09599761
申请日：2000-06-22
申请人： Kamalesh K. Srivastava , Peter C. Wade , William H. Brearley , Jonathan H. Griffith
发明人： Kamalesh K. Srivastava , Peter C. Wade , William H. Brearley , Jonathan H. Griffith
IPC分类号： C03C1500
CPC分类号： H01J37/3244 , H01J37/32623
摘要： RIE processing chambers includes arrangements of gas outlets which force gas-flow-shadow elimination. Means are provided to control and adjust the direction of gases to the outlet to modify and control the direction of plasma flow at the wafer surface during processing. Means are provided to either move the exhaust paths for exhaust gases or to open and close exhaust paths sequentially, in a controlled manner, to modify flow directions of ions in the etching plasma. A combination of rotation/oscillation of a magnetic field imposed on the RIE chamber can be employed by rotation of permanent magnetic dipoles about the periphery of the RIE chamber or by controlling current through a coil wrapped around the periphery of the RIE process chamber to enhance the removal of the residues attributable to gas-flow-shadows formed by linear ion paths in the plasma.
摘要翻译： RIE处理室包括迫使气体流动阴影消除的气体出口的布置。提供了用于控制和调节气体到出口的方向的装置，以在处理期间修改和控制晶片表面处的等离子体流动的方向。提供装置以便以排气的方式移动排气路径或以受控的方式依次打开和关闭排气路径，以改变蚀刻等离子体中离子的流动方向。施加在RIE室上的磁场的旋转/振荡的组合可以通过围绕RIE室的周边的永久磁偶极子的旋转或通过围绕RIE处理室的周边缠绕的线圈进行控制来增强去除归因于等离子体中的线性离子路径形成的气流阴影的残留物。

2. 发明授权

US07645700B2 Dry etchback of interconnect contacts 有权
标题翻译：互连触点的干蚀刻
公开(公告)号：US07645700B2
公开(公告)日：2010-01-12
申请号：US11946922
申请日：2007-11-29
申请人： Theodorus E Standaert , William H Brearley , Stephen E Greco , Sujatha Sankaran
发明人： Theodorus E Standaert , William H Brearley , Stephen E Greco , Sujatha Sankaran
IPC分类号： H01L21/44
CPC分类号： H01L21/76808 , H01L21/31116 , H01L21/32136 , H01L21/76847 , H01L21/76877 , H01L21/76883 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.
摘要翻译：具有降低的接触电阻和改善的可靠性的复合螺柱接触界面的方法和结构。使用包含含氟气体的选择性干蚀刻。在M1 RIE工艺过程中或之后，通过部分干法蚀刻钨触点来降低接触电阻。然后在M1衬套/电镀工艺期间将凹陷接触件金属化。钨接触高度在完全成型后减小。

3. 发明授权

US07323410B2 Dry etchback of interconnect contacts 有权
标题翻译：互连触点的干蚀刻
公开(公告)号：US07323410B2
公开(公告)日：2008-01-29
申请号：US11161538
申请日：2005-08-08
申请人： Theodorus E. Standaert , William H. Brearley , Stephen E. Greco , Sujatha Sankaran
发明人： Theodorus E. Standaert , William H. Brearley , Stephen E. Greco , Sujatha Sankaran
IPC分类号： H01L21/44
CPC分类号： H01L21/76808 , H01L21/31116 , H01L21/32136 , H01L21/76847 , H01L21/76877 , H01L21/76883 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.
摘要翻译：具有降低的接触电阻和改善的可靠性的复合螺柱接触界面的方法和结构。使用包含含氟气体的选择性干蚀刻。在M1 RIE工艺过程中或之后，通过部分干法蚀刻钨触点来降低接触电阻。然后在M1衬套/电镀工艺期间将凹陷接触件金属化。钨接触高度在完全成型后减小。

4. 发明授权

US06293457B1 Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization 有权
标题翻译：用于铜镀金属CMOS器件的BLM钛 - 钨合金蚀刻的集成方法
公开(公告)号：US06293457B1
公开(公告)日：2001-09-25
申请号：US09590119
申请日：2000-06-08
申请人： Kamalesh K. Srivastava , Jonathan H. Griffith , Mary C. Cullinan-Scholl , William H. Brearley , Peter C. Wade
发明人： Kamalesh K. Srivastava , Jonathan H. Griffith , Mary C. Cullinan-Scholl , William H. Brearley , Peter C. Wade
IPC分类号： B23K3102
CPC分类号： H01L24/05 , C23F1/26 , H01L21/76804 , H01L24/03 , H01L24/11 , H01L24/81 , H01L2224/0347 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05082 , H01L2224/05624 , H01L2224/05647 , H01L2224/1147 , H01L2224/11912 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01016 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01059 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/3011 , H01L2924/00014
摘要： Form a solder connector on a semiconductor device starting with a first step of forming at least one dielectric layer over a doped semiconductor substrate. Then form a hole through the dielectric layer down to the semiconductor substrate. Form a metal conductor in the hole. Form intermediate layers over the metal conductor and the dielectric layer. Then form a tapered opening down to the surface of the metal conductor. Form BLM layers including a titanium-tungsten (TiW) layer over the metal conductor and the dielectric layer with the remainder of the BLM layers being formed over the TiW layer. Form a mask over the top surface of the BLM layers with a patterning through hole located above the metal conductor exposing a portion of the surface of the BLM layers. Plate a C4 solder bump on the BLM layers in the patterning hole. Remove the mask. Wet etch away the BLM layers aside from the solder bump leaving a residual TiW layer over the dielectric layer. Perform a dry etching process to remove the residual TiW layer aside from the solder bump. Then, end the dry etching when the end point has been reached. Finally, heat the solder bump in a reflow process to form a C4 solder ball.
摘要翻译：在半导体器件上形成焊料连接器，从在掺杂半导体衬底上形成至少一个电介质层的第一步骤开始。然后通过介电层形成一个穿过半导体衬底的孔。在孔中形成金属导体。在金属导体和电介质层上形成中间层。然后形成锥形开口，直到金属导体的表面。在金属导体上形成包括钛 - 钨（TiW）层的BLM层，其中剩余的BLM层形成在TiW层上。在BLM层的顶表面上形成掩模，其中图案化通孔位于金属导体上方，露出BLM层表面的一部分。在图案化孔中的BLM层上贴上C4焊料凸块。取下面具。湿式蚀刻除了焊料凸块之外的BLM层，在电介质层上留下残留的TiW层。执行干蚀刻工艺以除去焊料凸块之外的残余TiW层。然后，当达到终点时结束干蚀刻。最后，在回流焊过程中加热焊料凸块以形成C4焊球。

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