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1. 发明授权

US5444015A Larce scale IC personalization method employing air dielectric structure for extended conductors 失效
标题翻译： Larce尺寸IC个性化方法采用空气电介质结构用于扩展导体
公开(公告)号：US5444015A
公开(公告)日：1995-08-22
申请号：US225685
申请日：1994-04-11
申请人： John M. Aitken , Klaus D. Beyer , Billy L. Crowder , Stephen E. Greco
发明人： John M. Aitken , Klaus D. Beyer , Billy L. Crowder , Stephen E. Greco
IPC分类号： H01L27/04 , H01L21/768 , H01L21/822 , H01L23/522 , H01L21/28
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002
摘要： Fabrication methods for forming a network of walls concurrently with the formation of studs for interconnecting plural device layers of a large scale integrated circuit device permits aggressive reduction of the average dielectric constant of air dielectric structures. Wall sections may be positioned to laterally support high aspect ratio connecting studs with a network of open or closed polygons. Wall patterns may also be open from layer to layer to allow formation of large scale air dielectric structures over a plurality of layers in a single material removal step. A wide range of shear strengths and reductions of average dielectric constant can be achieved even within a single device layer of a large scale integrated circuit and exploited to meet circuit design and device fabrication process requirements.
摘要翻译：用于形成用于互连大规模集成电路器件的多个器件层的螺柱的壁的形成网络的制造方法允许大大降低空气电介质结构的平均介电常数。壁部分可以被定位成横向支撑具有开放或闭合多边形网络的高纵横比连接螺柱。壁图案也可以从一层开放，以允许在单个材料去除步骤中在多个层上形成大规模空气介电结构。即使在大规模集成电路的单个器件层内，也可以获得宽范围的剪切强度和平均介电常数的降低，并被用于满足电路设计和器件制造工艺要求。

2. 发明授权

US5530290A Large scale IC personalization method employing air dielectric structure for extended conductor 失效
标题翻译：使用扩展导体的空气电介质结构的大规模IC个性化方法
公开(公告)号：US5530290A
公开(公告)日：1996-06-25
申请号：US226103
申请日：1994-04-11
申请人： John M. Aitken , Klaus D. Beyer , Billy L. Crowder , Stephen E. Greco
发明人： John M. Aitken , Klaus D. Beyer , Billy L. Crowder , Stephen E. Greco
IPC分类号： H01L27/04 , H01L21/768 , H01L21/822 , H01L23/522 , H01L23/528 , H01L23/535
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002
摘要： Fabrication methods for forming a network of walls concurrently with the formation of studs for interconnecting plural device layers of a large scale integrated circuit device permits aggressive reduction of the average dielectric constant of air dielectric structures. Wall sections may be positioned to laterally support high aspect ratio connecting studs with a network of open or closed polygons. Wall patterns may also be open from layer to layer to allow formation of large scale air dielectric structures over a plurality of layers in a single material removal step. A wide range of shear strengths and reductions of average dielectric constant can be achieved even within a single device layer of a large scale integrated circuit and exploited to meet circuit design and device fabrication process requirements.
摘要翻译：用于形成用于互连大规模集成电路器件的多个器件层的螺柱的壁的形成网络的制造方法允许大大降低空气电介质结构的平均介电常数。壁部分可以被定位成横向支撑具有开放或闭合多边形网络的高纵横比连接螺柱。壁图案也可以从一层开放，以允许在单个材料去除步骤中在多个层上形成大规模空气介电结构。即使在大规模集成电路的单个器件层内，也可以获得宽范围的剪切强度和平均介电常数的降低，并被用于满足电路设计和器件制造工艺要求。

3. 发明授权

US5391911A Reach-through isolation silicon-on-insulator device 失效
标题翻译：隔离绝缘体上的隔离器器件
公开(公告)号：US5391911A
公开(公告)日：1995-02-21
申请号：US231100
申请日：1994-04-22
申请人： Klaus D. Beyer , Andrie S. Yapsir
发明人： Klaus D. Beyer , Andrie S. Yapsir
IPC分类号： H01L21/764 , H01L21/76 , H01L21/762 , H01L27/12 , H01L27/04
CPC分类号： H01L21/76264 , H01L21/76289 , Y10S148/05 , Y10S148/164
摘要： A method and the resulting product for isolating lightly doped silicon islands from each other and from a common substrate. The substrate is covered with a first heavily doped epi layer. The first layer is covered with a lightly doped second epi layer. A pair of spaced deep trenches are provided which extend from the top surface of the second layer, through the first layer and into the substrate. The interior walls of the trenches are lined with oxide. A pair of heavily doped reach-through diffusions extending from said top surface to the first layer is oriented perpendicularly to the deep trenches and fully extends between the trenches. The heavily doped reach-through diffusions and the contiguous first layer are removed by a single anisotropic etching step to yield silicon islands isolated by air except where the islands contact the oxide-lined deep trenches. The air isolation preferably is partially replaced with other dielectric material.
摘要翻译：一种方法和所得到的产品，用于将共同的衬底彼此分离轻掺杂的硅岛。衬底被第一重掺杂外延层覆盖。第一层被轻掺杂的第二外延层覆盖。提供一对间隔的深沟槽，其从第二层的顶表面延伸穿过第一层并进入衬底。沟槽的内壁衬有氧化物。从所述顶表面延伸到第一层的一对重掺杂的贯穿扩散层垂直于深沟槽定向并在沟槽之间完全延伸。通过单个各向异性蚀刻步骤去除重掺杂的通孔扩散和相邻的第一层，以产生除空气与氧化物衬里的深沟槽接触的空气，由空气隔离。空气隔离优选地部分地被其它介电材料替代。

4. 发明授权

US5366923A Bonded wafer structure having a buried insulation layer 失效
公开(公告)号：US5366923A
公开(公告)日：1994-11-22
申请号：US164094
申请日：1993-12-08
申请人： Klaus D. Beyer , Chang-Ming Hsieh , Louis L. Hsu , Tsorng-Dih Yuan
发明人： Klaus D. Beyer , Chang-Ming Hsieh , Louis L. Hsu , Tsorng-Dih Yuan
IPC分类号： H01L21/02 , H01L21/20 , H01L21/76 , H01L21/762 , H01L27/12
CPC分类号： H01L21/76264 , H01L21/2007 , H01L21/76275 , H01L21/76283 , H01L21/76286 , Y10S148/012 , Y10S148/135
摘要： A wafer structure and a method of making the same, upon which semiconductor devices may be formed, comprises first and second wafers. The first wafer comprises a first substrate having a thin oxide layer formed on a bottom surface thereof, the first substrate having a characteristic thermal expansion coefficient. The second wafer comprises a second substrate having an insulation layer formed on a top surface thereof, the insulation layer having a characteristic thermal expansion coefficient substantially matched with the characteristic thermal expansion coefficient of the first substrate and further having a high thermal conductivity. The second wafer further comprises a thin oxide layer formed on a top surface of the insulation layer, wherein the first thin oxide layer of the first wafer is bonded to the second thin oxide layer of the second wafer.

5. 发明授权

US5098856A Air-filled isolation trench with chemically vapor deposited silicon dioxide cap 失效
标题翻译：充气隔离沟槽，化学气相沉积二氧化硅盖
公开(公告)号：US5098856A
公开(公告)日：1992-03-24
申请号：US717267
申请日：1991-06-18
申请人： Klaus D. Beyer , Louis L. Hsu , Subodh K. Kulkarni
发明人： Klaus D. Beyer , Louis L. Hsu , Subodh K. Kulkarni
IPC分类号： H01L21/76 , H01L21/764
CPC分类号： H01L21/764
摘要： A process for forming air-filled isolation trenches in a semiconductor substrate by a conformal chemical vapor deposition (CVD) of a silicon dioxide layer over the passivated surface of the semiconductor substrate in which intersecting trenches have been formed and partially filled with a material that can subsequentially be removed from under the CVD silicon dioxide layer, such materials include water soluble glasses and polymeric materials, such as a polyimide. The CVD silicon dioxide is etched back to the passivated surface of the semiconductor substrate, forming openings in the layer at the trench intersections that extend to the trench fill material. The fill material is removed through these openings. A CVD silicon dioxide layer is deposited to fill the openings, leaving a silicon dioxide cap bridging the air-filled trench. Water soluble glasses that may be used to fill the trench include BSG glass (B.sub.2 O.sub.3 content greater than 55%) and germanosilicate glass (GeO.sub.2 content greater than 50%). A polymer fill, such as a polyimide, if used, may be removed by plasma etching in O.sub.2.

6. 发明授权

US06709951B2 Oxynitride shallow trench isolation and method of formation 有权
标题翻译：氮氧化物浅沟槽隔离和形成方法
公开(公告)号：US06709951B2
公开(公告)日：2004-03-23
申请号：US10246252
申请日：2002-09-18
申请人： Klaus D. Beyer , Fen F. Jamin , Patrick R. Varekamp
发明人： Klaus D. Beyer , Fen F. Jamin , Patrick R. Varekamp
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.
摘要翻译：氧氮化物材料用于在集成电路结构中形成浅沟槽隔离区。氧氮化物可以用于沟槽衬垫和沟槽填充材料。氧氮化物衬垫通过氮化最初形成的氧化物沟槽衬垫而形成。氧氮化物沟槽填充材料通过直接沉积SiH 4和O 2的高密度等离子体（HDP）氧化物混合物并且将等量的NH 3加入到等离子体混合物中而形成。所得到的氮氧化物结构例如通过湿法蚀刻对沟槽填充侵蚀的抵抗性更高，但是对周围硅的应力最小。为了进一步减少应力，可以通过改变等离子体混合物中的O 2与NH 3的比例来改变氮浓度，从而在填充材料的顶部的氮浓度最大。

7. 发明授权

US5306659A Reach-through isolation etching method for silicon-on-insulator devices 失效
标题翻译：绝缘体上硅器件的透光隔离蚀刻方法
公开(公告)号：US5306659A
公开(公告)日：1994-04-26
申请号：US37855
申请日：1993-03-29
申请人： Klaus D. Beyer , Andrie S. Yapsir
发明人： Klaus D. Beyer , Andrie S. Yapsir
IPC分类号： H01L21/764 , H01L21/76 , H01L21/762 , H01L27/12
CPC分类号： H01L21/76264 , H01L21/76289 , Y10S148/05 , Y10S148/164
摘要： A method and the resulting product for isolating lightly doped silicon islands from each other and from a common substrate. The substrate is covered with a first heavily doped epi layer. The first layer is covered with a lightly doped second epi layer. A pair of spaced deep trenches are provided which extend from the top surface of the second layer, through the first layer and into the substrate. The interior walls of the trenches are lined with oxide. A pair of heavily doped reach-through diffusions extending from said top surface to the first layer is oriented perpendicularly to the deep trenches and fully extends between the trenches. The heavily doped reach-through diffusions and the contiguous first layer are removed by a single anisotropic etching step to yield silicon islands isolated by air except where the islands contact the oxide-lined deep trenches. The air isolation preferably is partially replaced with other dielectric material.
摘要翻译：一种方法和所得到的产品，用于将共同的衬底彼此分离轻掺杂的硅岛。衬底被第一重掺杂外延层覆盖。第一层被轻掺杂的第二外延层覆盖。提供一对间隔的深沟槽，其从第二层的顶表面延伸穿过第一层并进入衬底。沟槽的内壁衬有氧化物。从所述顶表面延伸到第一层的一对重掺杂的贯穿扩散层垂直于深沟槽定向并在沟槽之间完全延伸。通过单个各向异性蚀刻步骤去除重掺杂的通孔扩散和相邻的第一层，以产生除空气与氧化物衬里的深沟槽接触的空气，由空气隔离。空气隔离优选地部分地被其它介电材料替代。

8. 发明授权

US4671851A Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique 失效
标题翻译：使用化学机械抛光技术在半导体晶片的表面去除突起的方法
公开(公告)号：US4671851A
公开(公告)日：1987-06-09
申请号：US791861
申请日：1985-10-28
申请人： Klaus D. Beyer , James S. Makris , Eric Mendel , Karen A. Nummy , Seiki Ogura , Jacob Riseman , Nivo Rovedo
发明人： Klaus D. Beyer , James S. Makris , Eric Mendel , Karen A. Nummy , Seiki Ogura , Jacob Riseman , Nivo Rovedo
IPC分类号： H01L21/76 , H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/3105 , H01L21/74 , H01L21/762 , H01L21/763
CPC分类号： H01L21/763 , H01L21/31053 , H01L21/743 , H01L21/76202
摘要： A chemical-mechanical (chem-mech) method for removing SiO.sub.2 protuberances at the surface of a silicon chip, such protuberances including "bird's heads". A thin etch stop layer of Si.sub.3 N.sub.4 is deposited onto the wafer surface, which is then chem-mech polished with a SiO.sub.2 water based slurry. The Si.sub.3 N.sub.4 acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si.sub.3 N.sub.4 layer located on the top and at the sidewalls of the "bird's heads" and the underlying SiO.sub.2 protuberances are removed to provide a substantially planar integrated structure.
摘要翻译：用于去除硅片表面的SiO 2突起的化学机械（化学机械）方法，包括“鸟头”的突起。将Si 3 N 4的薄的蚀刻停止层沉积在晶片表面上，然后用SiO 2水基浆料进行化学研磨。 Si 3 N 4仅在晶片表面的平面部分上用作抛光或蚀刻阻挡层。位于“鸟头”顶部和侧壁处的Si 3 N 4层的部分和下面的SiO 2突起被去除以提供基本平坦的整体结构。

9. 发明授权

US4069068A Semiconductor fabrication method for improved device yield by minimizing pipes between common conductivity type regions 失效
标题翻译：半导体制造方法，通过最小化公共导电类型区域之间的管道来提高器件产量
公开(公告)号：US4069068A
公开(公告)日：1978-01-17
申请号：US701789
申请日：1976-07-02
申请人： Klaus D. Beyer , Gobinda Das , Michael R. Poponiak , Tsu-Hsing Yeh
发明人： Klaus D. Beyer , Gobinda Das , Michael R. Poponiak , Tsu-Hsing Yeh
IPC分类号： H01L29/73 , H01L21/265 , H01L21/28 , H01L21/322 , H01L21/331 , H01L29/32
CPC分类号： H01L21/26506 , H01L21/26526 , H01L21/3221 , Y10S148/024
摘要： A method for fabricating bipolar semiconductor devices of large scale integration in which the formation of pipes, which result in shorts or leakages between two conductivity types of the semiconductor devices, is minimized. Prior to forming the emitters in the bipolar transistors, nucleation sites for crystallographic defects such as dislocation loops are formed in the base region near its surface. The emitters are then formed in base regions containing the nucleation sites and the sites are converted into electrically harmless dislocation loops during diffusion of the emitter impurity. Preferably, the nucleation sites are formed by implanting non-doping impurities, such as helium, neon, argon, krypton, xenon, silicon, and oxygen.
摘要翻译：一种用于制造大规模集成的双极性半导体器件的方法，其中导致在两种导电类型的半导体器件之间的短路或泄漏的管的形成被最小化。在双极晶体管中形成发射极之前，在其表面附近的基极区域中形成诸如位错环的晶体缺陷的成核位置。然后将发射体形成在含有成核位点的碱性区域中，并且在发射极杂质扩散期间将这些位点转化为电气无害位错环。优选地，通过注入非掺杂杂质如氦，氖，氩，氪，氙，硅和氧来形成成核位点。

10. 发明授权

US5405795A Method of forming a SOI transistor having a self-aligned body contact 失效
标题翻译：形成具有自对准体接触的SOI晶体管的方法
公开(公告)号：US5405795A
公开(公告)日：1995-04-11
申请号：US268380
申请日：1994-06-29
申请人： Klaus D. Beyer , Taqi N. Buti , Chang-Ming Hsieh , Louis L. Hsu
发明人： Klaus D. Beyer , Taqi N. Buti , Chang-Ming Hsieh , Louis L. Hsu
IPC分类号： H01L21/336 , H01L29/786 , H01L21/265
CPC分类号： H01L29/66772 , H01L29/41783 , H01L29/78612 , Y10S148/15
摘要： An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.
摘要翻译： SOI晶体管具有通过对门的延伸形成的自对准体接触，从而以最小的面积增加形成身体接触，并且还避免了将源连接到身体的需要，如通过身体的现有技术方案通过来源联系。身体接触孔通过提高源极和漏极以形成初始孔径而形成，沉积被蚀刻以形成孔限定侧壁的共形层并且使用这些侧壁蚀刻接触孔以限定支撑绝缘侧壁以隔离的侧壁支撑构件收集电极来自闸门和源极和漏极。

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