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1. 发明授权

US07323410B2 Dry etchback of interconnect contacts 有权
标题翻译：互连触点的干蚀刻
公开(公告)号：US07323410B2
公开(公告)日：2008-01-29
申请号：US11161538
申请日：2005-08-08
申请人： Theodorus E. Standaert , William H. Brearley , Stephen E. Greco , Sujatha Sankaran
发明人： Theodorus E. Standaert , William H. Brearley , Stephen E. Greco , Sujatha Sankaran
IPC分类号： H01L21/44
CPC分类号： H01L21/76808 , H01L21/31116 , H01L21/32136 , H01L21/76847 , H01L21/76877 , H01L21/76883 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.
摘要翻译：具有降低的接触电阻和改善的可靠性的复合螺柱接触界面的方法和结构。使用包含含氟气体的选择性干蚀刻。在M1 RIE工艺过程中或之后，通过部分干法蚀刻钨触点来降低接触电阻。然后在M1衬套/电镀工艺期间将凹陷接触件金属化。钨接触高度在完全成型后减小。

2. 发明授权

US07071099B1 Forming of local and global wiring for semiconductor product 有权
标题翻译：形成半导体产品的本地和全球接线
公开(公告)号：US07071099B1
公开(公告)日：2006-07-04
申请号：US10908623
申请日：2005-05-19
申请人： Stephen E. Greco , Theodorus E. Standaert
发明人： Stephen E. Greco , Theodorus E. Standaert
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76807 , H01L21/76838 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming different back-end-of-line (BEOL) wiring for different circuits on the same semiconductor product, i.e., wafer or chip, are disclosed. In one embodiment, the method includes simultaneously generating BEOL wiring over a first circuit using a dual damascene structure in a first dielectric layer, and BEOL wiring over a second circuit using a single damascene via structure in the first dielectric layer. Then, simultaneously generating BEOL wiring over the first circuit using a dual damascene structure in a second dielectric layer, and BEOL wiring over the second circuit using a single damascene line wire structure in the second dielectric layer. The single damascene via structure has a width approximately twice that of a via portion of the dual damascene structures and the single damascene line wire structure has a width approximately twice that of a line wire portion of the dual damascene structures. A semiconductor product having different width BEOL wiring for different circuits is also disclosed.
摘要翻译：公开了在同一半导体产品即晶片或芯片上形成用于不同电路的不同后端线（BEOL）布线的方法。在一个实施例中，该方法包括使用第一电介质层中的双镶嵌结构在第一电路上同时产生BEOL布线，以及使用第一电介质层中的单镶嵌通孔结构的第二电路上的BEOL布线。然后，使用第二电介质层中的双镶嵌结构同时在第一电路上产生BEOL布线，并且在第二电介质层中使用单个镶嵌线线结构在第二电路上生成BEOL布线。单个镶嵌通孔结构的宽度大约是双镶嵌结构的通孔部分的宽度的两倍，并且单镶嵌线结构的宽度大约是双镶嵌结构的线丝部分的宽度的两倍。还公开了一种用于不同电路的具有不同宽度的BEOL布线的半导体产品。

3. 发明授权

US08492268B2 IC having viabar interconnection and related method 有权
标题翻译： IC具有viabar互连及相关方法
公开(公告)号：US08492268B2
公开(公告)日：2013-07-23
申请号：US13410466
申请日：2012-03-02
申请人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
发明人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
IPC分类号： H01L23/52
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.
摘要翻译：一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar，在第二位置处连接到第一金属层的布线而不是第二金属层的布线。

4. 发明授权

US08484586B2 System and method of predicting problematic areas for lithography in a circuit design 有权
公开(公告)号：US08484586B2
公开(公告)日：2013-07-09
申请号：US13517811
申请日：2012-06-14
申请人： Timothy A. Brunner , Stephen E. Greco , Bernhard R. Liegl , Hua Xiang
发明人： Timothy A. Brunner , Stephen E. Greco , Bernhard R. Liegl , Hua Xiang
IPC分类号： G06F17/50 , G02B7/04 , H01L27/00
CPC分类号： G06F17/5045 , G03F1/144 , G03F1/36 , G03F1/70 , G03F7/705
摘要： A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

5. 发明申请

US20120164758A1 IC HAVING VIABAR INTERCONNECTION AND RELATED METHOD 有权
标题翻译：具有VIABAR互连的IC和相关方法
公开(公告)号：US20120164758A1
公开(公告)日：2012-06-28
申请号：US13410466
申请日：2012-03-02
申请人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
发明人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
IPC分类号： H01L21/66
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.
摘要翻译：一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar，在第二位置处连接到第一金属层的布线而不是第二金属层的布线。

6. 发明授权

US07439173B2 Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via 失效
标题翻译：使用垂直向上延伸的虚拟通孔增加IC中的电迁移寿命和电流密度
公开(公告)号：US07439173B2
公开(公告)日：2008-10-21
申请号：US11869044
申请日：2007-10-09
申请人： Stephen E. Greco , Chao-Kun Hu , Paul S. McLaughlin
发明人： Stephen E. Greco , Chao-Kun Hu , Paul S. McLaughlin
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.
摘要翻译：公开了一种具有增加的电迁移寿命和允许电流密度的集成电路及其形成方法。在一个实施例中，集成电路包括连接到至少一个功能通孔的导线，以及至少一个虚拟通孔，其具有与导电线电连接的第一下端，以及电连接（隔离）至任何导电线。每个虚拟通孔从导电线垂直向上延伸，并且去除快速扩散路径的一部分，即金属到电介质盖界面，其被金属对金属衬垫界面代替。因此，每个虚拟通孔可以减少金属扩散速率，从而增加电迁移寿命并允许增加电流密度。

7. 发明授权

US06479884B2 Interim oxidation of silsesquioxane dielectric for dual damascene process 有权
标题翻译：双重镶嵌工艺的倍半硅氧烷电介质的中间氧化
公开(公告)号：US06479884B2
公开(公告)日：2002-11-12
申请号：US09893786
申请日：2001-06-29
申请人： Robert Cook , Stephen E. Greco , John P. Hummel , Joyce Liu , Vincent J. McGahay , Rebecca Mih , Kamalesh Srivastava
发明人： Robert Cook , Stephen E. Greco , John P. Hummel , Joyce Liu , Vincent J. McGahay , Rebecca Mih , Kamalesh Srivastava
IPC分类号： H01L2358
CPC分类号： H01L21/76808 , H01L2221/1063
摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.
摘要翻译：抗蚀剂显影剂可以攻击一些先进的介电材料，例如可以用作集成电路芯片的表面和形成在介电材料表面上的布线层之间的绝缘体的倍半硅氧烷材料。通过进行抗蚀剂剥离或蚀刻工艺，其中将反应物材料从电介质材料外部供应或释放出来，可以形成非常薄的中间材料的表面保护覆盖层，其不能抵抗显影剂或多种其它材料这可能会损坏可流动的氧化物材料。因此，与芯片形成牢固的连接和通孔的双镶嵌工艺可以与具有特别低介电常数的先进电介质相兼容，以最小化导体电容并支持快速的信号传播和抗噪声性，即使导体彼此间隔紧密。

8. 发明授权

US06329280B1 Interim oxidation of silsesquioxane dielectric for dual damascene process 失效
公开(公告)号：US06329280B1
公开(公告)日：2001-12-11
申请号：US09311470
申请日：1999-05-13
申请人： Robert Cook , Stephen E. Greco , John P. Hummel , Joyce Liu , Vincent J. McGahay , Rebecca Mih , Kamalesh Srivastava
发明人： Robert Cook , Stephen E. Greco , John P. Hummel , Joyce Liu , Vincent J. McGahay , Rebecca Mih , Kamalesh Srivastava
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L2221/1063
摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

9. 发明授权

US08299622B2 IC having viabar interconnection and related method 有权
标题翻译： IC具有viabar互连及相关方法
公开(公告)号：US08299622B2
公开(公告)日：2012-10-30
申请号：US12186061
申请日：2008-08-05
申请人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
发明人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
IPC分类号： H01L23/52
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.
摘要翻译：一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar，在第二位置处连接到第一金属层的布线而不是第二金属层的布线。

10. 发明授权

US08239789B2 System and method of predicting problematic areas for lithography in a circuit design 有权
标题翻译：在电路设计中预测光刻问题区域的系统和方法
公开(公告)号：US08239789B2
公开(公告)日：2012-08-07
申请号：US13080148
申请日：2011-04-05
申请人： Timothy A. Brunner , Stephen E. Greco , Bernhard R. Liegl , Hua Xiang
发明人： Timothy A. Brunner , Stephen E. Greco , Bernhard R. Liegl , Hua Xiang
IPC分类号： G06F17/50 , G03F1/00 , G03C5/00
CPC分类号： G06F17/5045 , G03F1/144 , G03F1/36 , G03F1/70 , G03F7/705
摘要： A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.
摘要翻译：提供了一种系统和方法，其预测电路设计中的光刻的有问题的区域，更具体地，其使用来自建模工具的建模数据来准确地预测有问题的光刻区域。该方法包括识别模拟晶片的多个瓦片的表面高度，以及数学上模拟光刻工具以确定用于多个瓦片的曝光的最佳焦点平面。

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