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21. 发明授权

US5567645A Device isolation method in integrated circuits 失效
标题翻译：集成电路中的器件隔离方法
公开(公告)号：US5567645A
公开(公告)日：1996-10-22
申请号：US231705
申请日：1994-04-22
申请人： Sung-tae Ahn , Tai-su Park
发明人： Sung-tae Ahn , Tai-su Park
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762
CPC分类号： H01L21/76202
摘要： An improved method for performing a local oxidation of silicon (LOCOS) capable of forming a sufficient thickness of a field oxide film even in narrow isolation regions. After defining the isolation region, a first field oxide film is formed in the isolation region by means of a first field oxidation. A film formed of HTO, LTO or SOG, or a pre-oxide film formed of polysilicon is formed on the resultant product. Then, the film, oxide film or the pre-oxide film is removed by anisotropically etching with a dry etching process or a chemical mechanical process so as to be left only in the isolation region, which after a second field oxidation forms a second field oxide film. According to the present invention, the problems associated with the field oxide film thinning effect usually associated with the conventional LOCOS-series isolation method can be overcome by either making the isolation structure in narrow isolation regions have a total thickness which is equal to that in the wide isolation regions, or by making the former thicker than the latter.
摘要翻译：即使在狭窄的隔离区域中能够形成足够厚度的场氧化物膜的硅（LOCOS）的局部氧化的改进方法。在限定隔离区之后，通过第一场氧化在隔离区中形成第一场氧化物膜。在所得产物上形成由HTO，LTO或SOG形成的膜或由多晶硅形成的预氧化物膜。然后，通过用干蚀刻工艺或化学机械工艺进行各向异性蚀刻除去膜，氧化膜或预氧化物膜，以便仅留在隔离区域中，其在第二场氧化后形成第二场氧化物电影。根据本发明，通常与常规LOCOS系列隔离方法相关的场氧化膜薄化效应相关的问题可以通过使狭窄隔离区域中的隔离结构的总厚度等于或者通过使前者比后者更厚。

22. 发明授权

US07968442B2 Fin field effect transistor and method of fabricating the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US07968442B2
公开(公告)日：2011-06-28
申请号：US12459660
申请日：2009-07-06
申请人： Jong-hoon Kang , Tai-su Park , Dong-chan Kim , Yu-gyun Shin , Jeong-do Ryu , Seong-hoon Jeong
发明人： Jong-hoon Kang , Tai-su Park , Dong-chan Kim , Yu-gyun Shin , Jeong-do Ryu , Seong-hoon Jeong
IPC分类号： H01L21/28
CPC分类号： H01L29/7854 , H01L29/66795
摘要： A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode.
摘要翻译：翅片场效应晶体管包括从半导体衬底突出的鳍片，形成为覆盖鳍片的上表面和侧表面的栅极绝缘层，以及跨过鳍状物形成以覆盖栅极绝缘层的栅电极。鳍的上边缘是圆形的，使得通过栅电极集中地施加到鳍的上边缘的电场被分散。形成在鳍的上表面上的栅极绝缘层的一部分的厚度大于形成在鳍的侧表面上的栅极绝缘层的一部分的厚度，以便减少通过栅电极。

23. 发明申请

US20100109057A1 Fin field effect transistor and method of fabricating the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US20100109057A1
公开(公告)日：2010-05-06
申请号：US12459660
申请日：2009-07-06
申请人： Jong-hoon Kang , Tai-su Park , Dong-chan Kim , Yu-gyun Shin , Jeong-do Ryu , Seong-hoon Jeong
发明人： Jong-hoon Kang , Tai-su Park , Dong-chan Kim , Yu-gyun Shin , Jeong-do Ryu , Seong-hoon Jeong
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7854 , H01L29/66795
摘要： A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode.
摘要翻译：翅片场效应晶体管包括从半导体衬底突出的鳍片，形成为覆盖鳍片的上表面和侧表面的栅极绝缘层，以及跨过鳍状物形成以覆盖栅极绝缘层的栅电极。鳍的上边缘是圆形的，使得通过栅电极集中地施加到鳍的上边缘的电场被分散。形成在鳍的上表面上的栅极绝缘层的一部分的厚度大于形成在鳍的侧表面上的栅极绝缘层的一部分的厚度，以便减少通过栅电极。

24. 发明授权

US07148541B2 Vertical channel field effect transistors having insulating layers thereon 有权
标题翻译：其上具有绝缘层的垂直沟道场效应晶体管
公开(公告)号：US07148541B2
公开(公告)日：2006-12-12
申请号：US10780067
申请日：2004-02-17
申请人： Tai-su Park , Eui-Joon Yoon , U-In Chung , Si-Young Choi , Jong-Ho Lee
发明人： Tai-su Park , Eui-Joon Yoon , U-In Chung , Si-Young Choi , Jong-Ho Lee
IPC分类号： H01L27/01
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7854
摘要： A field effect transistor can include a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction. Related methods are also disclosed.
摘要翻译：场效应晶体管可以包括从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，以及在垂直沟道的侧壁上朝向衬底延伸到源极/漏极区域交界处晶体管还可以包括在离开衬底的侧壁上延伸超过绝缘层的氮化物层，在侧壁上延伸的第二绝缘层，其通过氮化物层与沟道分离，以及栅电极侧壁朝向衬底以超出源/漏区结。还公开了相关方法。

25. 发明申请

US20060134868A1 Double gate field effect transistor and method of manufacturing the same 失效
标题翻译：双栅场效应晶体管及其制造方法
公开(公告)号：US20060134868A1
公开(公告)日：2006-06-22
申请号：US11316307
申请日：2005-12-21
申请人： Jae-Man Yoon , Dong-gun Park , Gyo-young Jin , Yoshida Makoto , Tai-su Park
发明人： Jae-Man Yoon , Dong-gun Park , Gyo-young Jin , Yoshida Makoto , Tai-su Park
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7851 , H01L21/823437 , H01L21/823481 , H01L21/84 , H01L27/1203 , H01L29/66795
摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.
摘要翻译：提供双栅场效应晶体管及其制造方法。制造双栅场效应晶体管的方法包括通过蚀刻硅衬底形成所需的散热片，通过绝缘材料如氮化硅掩蔽所得产物，通过使用氮化硅形成用于器件隔离的沟槽区域和STI膜掩模，在除去硬掩模之后在翅片的两个表面上形成栅极氧化膜，并形成栅极线。因此，当在没有突出的翅片形成的基板上形成厚的氧化硅膜时，通过在基板上施加高于阈值电压的电压，在氧化硅膜下形成不需要的通道。

26. 发明授权

US06627514B1 Semiconductor device having a Y-shaped isolation layer and simplified method for manufacturing the Y-shaped isolation layer to prevent divot formation 失效
标题翻译：具有Y形隔离层的半导体器件和用于制造Y形隔离层的简化方法以防止形成树脂
公开(公告)号：US06627514B1
公开(公告)日：2003-09-30
申请号：US09710225
申请日：2000-11-10
申请人： Tai-su Park , Kyung-won Park , Sung-jin Kim
发明人： Tai-su Park , Kyung-won Park , Sung-jin Kim
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A semiconductor device having a Y-shaped isolation layer and a method for manufacturing the same are provided. The semiconductor device includes a Y-shaped isolation layer, which comprises side walls characterized by first and second slopes on the sides of the isolation layer. The method for manufacturing the isolation layer includes the step of forming a trench in a semiconductor substrate using a photoresist pattern as an etching mask. Next, a thermal oxide film is formed on the surface of the semiconductor substrate, and then a thin nitride liner is formed on the thermal oxide film. The nitride liner prevents oxidation of the side wall of the trench and also acts as a planarization stop layer. Thereafter, a gap-filling isolation layer is formed to fill the trench such that the nitride liner is separated or thinner at the upper corners of the trench. Next, the gap-filling isolation layer is planarized using the nitride liner as a planarization stop layer. The nitride liner used as the planarization stop layer is removed. According to the present invention, formation of a divot at the boundary between an isolation region and an active region can be prevented.
摘要翻译：提供了具有Y形隔离层的半导体器件及其制造方法。该半导体器件包括Y形隔离层，其包括以隔离层侧面上的第一和第二斜面为特征的侧壁。用于制造隔离层的方法包括使用光致抗蚀剂图案作为蚀刻掩模在半导体衬底中形成沟槽的步骤。接下来，在半导体衬底的表面上形成热氧化膜，然后在热氧化膜上形成薄氮化物衬垫。氮化物衬垫防止沟槽的侧壁的氧化并且还用作平坦化停止层。此后，形成间隙填充隔离层以填充沟槽，使得氮化物衬垫在沟槽的上角分离或更薄。接下来，使用氮化物衬垫作为平坦化停止层来平坦化间隙填充隔离层。用作平坦化停止层的氮化物衬垫被去除。根据本发明，可以防止在隔离区域和有源区域之间的边界处形成边界。

27. 发明授权

US06465866B2 Trench isolation regions having trench liners with recessed ends 有权
标题翻译：具有凹槽端的沟槽衬套的沟槽隔离区
公开(公告)号：US06465866B2
公开(公告)日：2002-10-15
申请号：US09911096
申请日：2001-07-23
申请人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
发明人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.
摘要翻译：一种沟槽隔离结构，其通过对沟槽的顶部边缘进行舍入并增加在沟槽的顶部边缘处的氧化量，具有沟槽隔离结构的半导体器件和防止沟槽隔离结构的半导体器件，从而防止晶体管的隆起现象和反向窄宽度效应提供沟槽隔离方法。在这种沟槽隔离方法中，在半导体衬底的非有源区中形成沟槽。在沟槽的内壁上形成厚度为10至150埃的内壁氧化膜。在内壁氧化膜的表面上形成衬垫。沟槽填充有电介质膜。蚀刻衬垫的一部分，使得氮化硅衬垫的顶端从半导体衬底的表面凹陷。

28. 发明授权

US6083808A Method for forming a trench isolation in a semiconductor device 有权
标题翻译：在半导体器件中形成沟槽隔离的方法
公开(公告)号：US6083808A
公开(公告)日：2000-07-04
申请号：US160094
申请日：1998-09-25
申请人： Yu-Gyun Shin , Han-Sin Lee , Tai-su Park , Moon-Han Park
发明人： Yu-Gyun Shin , Han-Sin Lee , Tai-su Park , Moon-Han Park
IPC分类号： H01L21/76 , H01L21/28 , H01L21/762
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A method for forming a trench isolation in a semiconductor device is provided in which a first heat treatment process is conducted on a thermal oxide layer previously formed in a trench at temperature range from about 1000.degree. C. to 1200.degree. C. for about 1 to 8 hours so as to remove defects in a semiconductor substrate and oxygen impurities within the semiconductor substrate resulting from a step of forming the trench in the semiconductor substrate. As a result, a subsequent second heat treatment process for densifying a trench filling material such as a CVD oxide layer can be performed at lower temperature of about 1000.degree. C. to 1050.degree. C., as compared with the temperature of the first annealing of the thermal oxide layer, thereby reducing distortions of the semiconductor substrate and reducing current leakages.
摘要翻译：提供了一种在半导体器件中形成沟槽隔离的方法，其中对预先形成在沟槽中的热氧化层进行第一热处理工艺，温度范围为约1000℃至1200℃，约1至 8小时，以便从半导体衬底中形成沟槽的步骤得到半导体衬底中的缺陷和半导体衬底内的氧杂质。结果，与在第一次退火温度相比，可以在约1000℃至1050℃的较低温度下进行用于致密化CVD氧化物层的沟槽填充材料的随后的第二热处理工艺热氧化层，从而减少半导体衬底的变形并减少电流泄漏。

29. 发明授权

US5902127A Methods for forming isolation trenches including doped silicon oxide 失效
标题翻译：用于形成包括掺杂氧化硅的隔离沟槽的方法
公开(公告)号：US5902127A
公开(公告)日：1999-05-11
申请号：US742950
申请日：1996-10-31
申请人： Tai-su Park
发明人： Tai-su Park
IPC分类号： H01L21/76 , H01L21/265 , H01L21/762
CPC分类号： H01L21/76232 , Y10S148/05
摘要： A method for forming a microelectronic structure includes the steps of forming a trench in a substrate and forming an insulating layer which fills the trench and covers the substrate. Ions can be implanted into the insulating layer which decrease an etch rate of the insulating layer, and portions of the insulating layer on the substrate can be removed while maintaining the insulating layer in the trench. In addition, the step of forming the insulating layer can include forming an undoped oxide layer on the substrate and forming a doped oxide layer on the undoped oxide layer wherein a void is formed in the doped oxide layer. The void can thus be reduced by reflowing the doped oxide layer.
摘要翻译：一种形成微电子结构的方法包括以下步骤：在衬底中形成沟槽并形成填充沟槽并覆盖衬底的绝缘层。可以将离子注入到绝缘层中，这降低了绝缘层的蚀刻速率，并且可以在保持沟槽中的绝缘层的同时去除衬底上的绝缘层的部分。此外，形成绝缘层的步骤可以包括在衬底上形成未掺杂的氧化物层，并且在未掺杂的氧化物层上形成掺杂的氧化物层，其中在掺杂氧化物层中形成空隙。因此可以通过回流掺杂的氧化物层来减小空隙。

30. 发明授权

US5858858A Annealing methods for forming isolation trenches 失效
标题翻译：用于形成隔离沟的退火方法
公开(公告)号：US5858858A
公开(公告)日：1999-01-12
申请号：US729453
申请日：1996-10-11
申请人： Tai-su Park , Moon-han Park , Yu-gyun Shin , Han-sin Lee
发明人： Tai-su Park , Moon-han Park , Yu-gyun Shin , Han-sin Lee
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224
摘要： A method for forming a microelectronic structure includes the steps of forming a mask layer on a substrate, forming a trench in the exposed portion of the substrate, forming a layer of an insulating material which fills the trench and covers the mask layer, and annealing the insulating material at a temperature of at least about 1,150.degree. C. The annealing step can be performed for a period of time of about .5 hours to about 8 hours, and the annealing step can be performed in an inert atmosphere.
摘要翻译：一种形成微电子结构的方法包括以下步骤：在衬底上形成掩模层，在衬底的暴露部分形成沟槽，形成填充沟槽并覆盖掩模层的绝缘材料层，并退火绝缘材料在至少约1150℃的温度下进行。退火步骤可以进行约0.5小时至约8小时的时间，退火步骤可以在惰性气氛中进行。

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